COP8FG datasheet(19/59 Pages) NSC

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6.0 Timers (Continued)

•

Timing the width of the internal power-on-reset

The IDLE Timer T0 can generate an interrupt when the

twelfth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 2.731 ms at the maximum

clock frequency (t

C = 0.67 µs). A control flag T0EN allows the

interrupt from the twelfth bit of Timer T0 to be enabled or dis-

abled. Setting T0EN will enable the interrupt, while resetting

it will disable the interrupt.

6.2 TIMER T1, TIMER T2 and TIMER T3

Each device have a set of three powerful timer/counter

blocks, T1, T2 and T3. Since T1, T2, and T3 are identical, all

comments are equally applicable to any of the three timer

blocks which will be referred to as Tx.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

6.2.1 Mode 1. Processor Independent PWM Mode

One of the timer’s operating modes is the Processor Inde-

pendent PWM mode. In this mode, the timer generates a

“Processor Independent” PWM signal because once the

timer is setup, no more action is required from the CPU

which translates to less software overhead and greater

throughput. The user software services the timer block only

when the PWM parameters require updating. This capability

is provided by the fact that the timer has two separate 16-bit

reload registers. One of the reload registers contains the

“ON” timer while the other holds the “OFF” time. By contrast,

a microcontroller that has only a single reload register re-

quires an additional software to update the reload value (al-

ternate between the on-time/off-time).

The timer can generate the PWM output with the width and

duty cycle controlled by the values stored in the reload reg-

isters. The reload registers control the countdown values

and the reload values are automatically written into the timer

when it counts down through 0, generating interrupt on each

reload. Under software control and with minimal overhead,

the PMW outputs are useful in controlling motors, triacs, the

intensity of displays, and in providing inputs for data acquisi-

tion and sine wave generators.

In this mode, the timer Tx counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

Figure 16 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

6.2.2 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

DS101116-46

FIGURE 16. Timer in PWM Mode

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