Revision 3.2

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3.3

TIMING SIGNALS AND PANEL CLOCK

The CS9210 controls the generation of the flat panel tim-

ing signals via internal counters that count pixels as they

are output to the display. When the last pixel of a line is

output, the LP signal is asserted. The duration of the LP is

programmable via the LP Start and End registers at Index

0Ch-0Fh has shown in Table 3-3. Certain panels require

extra LPs at the end of a frame scan. This requirement is

also supported. The FLM output is asserted after a verti-

cal sync has occurred and the first pixel line, while

ENA_DISP is active, has begun. Position and duration of

the FLM pulse is also programmable via the FLM Start

and End registers at Index 10h-13h as shown in Table 3-3.

The CS9210 generates the STN panel clock. Since frac-

tional pixels are generally sent on the pixel bus to STN

panels, the ability to control the SHFCLK signal on a pixel-

to-pixel basis is provided to modulate the panel clock duty

cycle. Generally, for 16-bit DSTNs, the panel clock is the

DOTCLK divided by four with every fourth pulse masked

off (three SHFCLKs for four DOTCLK/4s). Programmable

options provide support for a wide range of panels.

3.4

SIMULTANEOUS DISPLAY

Theproblem with displaying pixeldatatobothaCRT

screen and a dual-scan STN panel at the same time, is

that both the upper and lower halves of a dual-scan STN

panel screen must be written at the same time. For a dual-

scan STN panel, pixel data for two horizontal scan lines is

written to the panel at the same time, one scan line to the

upper half of the panel and one scan line to the lower half

of the panel. This differs from the order that pixel data is

written to a CRT screen, where the pixel data for one hori-

zontal scan line at a time is written to the screen, starting

with the scan line at the top of the screen and ending at

the bottom of the screen.

Designs which incorporate the CS9210 are able to sup-

port simultaneous display with a dual-scan STN panel and

CRT. The CS9210 stores an entire frame of pixel data in

one of the external DRAM frame buffers, and then reor-

ders the pixel data stream to include pixel data for both

the upper and lower halves of the screen before sending

the data out to the panel. The data in the DRAM buffer

has already been frame-rate-modulated and/or dithered, if

necessary, and packed as three bits per pixel.

Simultaneous display is supported with both the panel

and CRT in the same mode and refresh rate. In this mode,

the refresh rate should be set as high as possible while

maintaining compatibility with established monitor timing

standards (typically 72-75 Hz). The same pixel input data

is fed to the CRT and the CS9210 simultaneously. As the

data comes into the CS9210, it is stored in one of the

external DRAMframe buffers. At thesametimedatais

being stored for the current frame, the CS9210 is reading

pixel data for the previous frame from the other external

DRAM frame buffer and sending it out on the flat panel

interface.

Table 3-3. Timing Related Registers

Bit

Description

Index 0Ch-0Dh

LP Start Register (R/W)

Reset Value = 005Ah

15:12

Reserved: Must be set to 0.

11:0

LP Start: 12-bit value that specifies the number of DOTCLK cycles to the start of the next LP pulse from the falling edge

of the last LP before internal VSYNC. (Refer to Figure 4-1.)

Index 0Eh-0Fh

LP End Register (R/W)

Reset Value = 0075h

15:12

Reserved: Must be set to 0.

11:0

LP End: 12-bit value that specifies the number of DOTCLK cycles in duration for updating one line of the LCD panel. This

value is used only in 1X Refresh Mode (Index 02h[5] = 0). (Refer to Figure 4-1.)

Index 10h-11h

FLM Start Register (R/W

Reset Value = 0020h

15:12

Reserved: Must be set to 0.

11:0

FLM Start — 12-bit value that specifies the number of DOTCLK cycles to the start of an FLM pulse from the internal

VSYNC signal rising edge. (Refer to Figure 4-1.)

Index 12h-13h

FLM End Register (R/W)

Reset Value = 0010h

15:12

Reserved: Must be set to 0.

11:0

FLM End: 12-bit value that specifies the number of DOTCLK cycles to the falling edge of the FLM pulse from the falling

edge of the first LP after the FLM pulse started. (Refer to Figure 4-1.)