Copyright © 2016 Future Technology Devices International Limited

13

FT600Q-FT601Q IC DatasheetDatasheet

Version 1.02

Doc ument N o.: FT _001118

C learance N o.: FT DI#424

The waveform below shows a master read transaction of 10 bytes with FIFO data exhausted first at

channel 1. There are turn-a-round cycles for DATA[7:0], DATA[31:16] and BE[3:0] after command phase

and at the end of the data transaction. The BE[3:0] shows that the lower 2 bytes in D2 are valid at the

last word strobe in this transaction.

Figure 4.1 Multi-Channel FIFO mode master read transaction 1

The waveform below shows a master read transaction for 12 valid bytes at channel 1, where the bus

master terminates the transaction. There are turn-a-round cycles for DATA[7:0], DATA[31:16] and

BE[3:0] after the command phase and at the end of the data transaction.

* The data is valid when WR_N and RXF_N are both active.

Figure 4.2 Multi-Channel FIFO mode master read transaction 2

⃰In Multi-channel FIFO mode master read operation, the bus master shall be able to read out the

maximum possible data in the RX FIFO in one read transaction, i.e. when the FT600 or FT601 is

configured in the 1 channel Multi-channel FIFO mode, the bus master shall be able to read out 4 KB in

if the bus master expects the data to be transferred over USB bus in the maximum possible packet length, it

should write the data to the FIFO in a single bus transaction.

E.g. Consider a USB 3.0 super-speed connection with a packet size is 1 KB, and a FIFO size of 4 KB.

IDLE

Command

phase

Data output

Bus turn

around

h’f