COP8CCR9KMT7 datasheet(54/84 Pages) NSC

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15.0 A/D Converter (Continued)

15.1.1.3 Mode Select

This 1-bit field is used to select the mode of operation (single

ended or differential) as shown in the following Table 22.

TABLE 22. A/D Conversion Mode Selection

ADMOD

Mode

Single Ended Mode

Differential Mode

15.1.1.4 Prescaler Select

This 1-bit field is used to select one of two prescaler clocks

for the A/D Converter. The following Table 23 shows the

various prescaler options. Care must be taken, when select-

ing this bit, to keep the A/D clock frequency within the

specified range.

TABLE 23. A/D Converter Clock Prescale

PSC

Clock Select

MCLK Divide by 1

MCLK Divide by 16

15.1.1.5 Busy Bit

The ADBSY bit of the ENAD register is used to control

starting and stopping of the A/D conversion. When ADBSY is

cleared, the prescale logic is disabled and the A/D clock is

turned off, drawing minimal power. Setting the ADBSY bit

starts the A/D clock and initiates a conversion based on the

values currently in the ENAD register. Normal completion of

an A/D conversion clears the ADBSY bit and turns off the A/D

Converter.

If the user wishes to restart a conversion which is already in

progress, this can be accomplished only by writing a zero to

the ADBSY bit to stop the current conversion and then by

writing a one to ADBSY to start a new conversion. This can

be done in two consecutive instructions.

15.1.2 A/D Result Registers

There are two result registers for the A/D converter: the high

8 bits of the result and the low 2-bits of the result. The format

of these registers is shown in Figures 27, 28. Both registers

are read/write registers, but in normal operation, the hard-

ware writes the value into the register when the conversion is

complete and the software reads the value. Both registers

are undefined upon Reset. They hold the previous value until

a new conversion overwrites them. When reading ADRSTL,

bits 5-0 will read as 0.

TABLE 24. ADRSTH

Bit 7

Bit 0

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

TABLE 25. ADRSTL

Bit 7

Bit 0

Bit 1

Bit 0

00000

10137429

FIGURE 26. A/D with Single Ended Mux Output Feature Enabled

10137430

FIGURE 27. A/D with Differential Mux Output Feature Enabled

COP8CCR9KMT7 Datasheet(PDF) 54 Page - National Semiconductor (TI)

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