COP8SCR9KMT7 datasheet(41/80 Pages) NSC

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13.0 Power Saving Features

(Continued)

Software clears the CCKSEL bit to 0.

13.4.1 Dual Clock HALT Mode

The fully static architecture of this device allows the state of

the microcontroller to be frozen. This is accomplished by

stopping the high speed clock of the device during the HALT

mode. The processor can be forced to exit the HALT mode

and resume normal operation at any time. The low speed

clock remains on during HALT in the Dual Clock mode.

During normal operation, the actual power consumption de-

pends heavily on the clock speed and operating voltage

used in an application and is shown in the Electrical Speci-

fications. In the HALT mode, the device only draws a small

leakage current, plus current for the BOR feature (if en-

abled), plus the 32 kHz oscillator current, plus any current

necessary for driving the outputs. Since total power con-

sumption is affected by the amount of current required to

drive the outputs, all I/Os should be configured to draw

minimal current prior to entering the HALT mode, if possible.

13.4.1.1 Entering The Dual Clock Halt Mode

The device enters the HALT mode under software control

when the Port G data register bit 7 is set to 1. All processor

action stops in the middle of the next instruction cycle, and

power consumption is reduced to a very low level. In order to

expedite exit from HALT, the low speed oscillator is left

running when the device is Halted in the Dual Clock mode.

However, the Idle Timer will not be clocked.

13.4.1.2 Exiting The Dual Clock Halt Mode

When the HALT mode is entered by setting bit 7 of the Port

G data register, there is a choice of methods for exiting the

HALT mode: a chip Reset using the RESET pin or a Multi-

Input Wake-up. The Reset method and Multi-Input Wake-up

method can be used with any clock option.

13.4.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the

RESET input pin, takes the device out of the Dual Clock

mode and puts it into the High Speed mode.

13.4.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a

transition received on one of the available Wake-up pins.

The pins used and the types of transitions sensed on the

Multi-input pins are software programmable. For information

on programming and using the Multi-Input Wake-up feature,

refer to 13.6 MULTI-INPUT WAKE-UP.

A start-up delay is required between the device wake-up and

the execution of program instructions. The start-up delay is

mandatory, and is implemented whether or not the CLKDLY

bit is set. This is because all crystal oscillators and resona-

tors require some time to reach a stable frequency and full

operating amplitude.

If the start-up delay is used, the IDLE Timer (Timer T0)

provides a fixed delay from the time the clock is enabled to

the time the program execution begins. Upon exit from the

HALT mode, the IDLE Timer is enabled with a starting value

of 256 and is decremented with each instruction cycle using

the high speed clock. (The instruction clock runs at one-fifth

the frequency of the high speed oscillatory.) An internal

Schmitt trigger connected to the on-chip CKI inverter en-

sures that the IDLE Timer is clocked only when the high

speed oscillator has a large enough amplitude. (The Schmitt

trigger is not part of the oscillator closed loop.) When the

IDLE Timer underflows, the clock signals are enabled on the

chip, allowing program execution to proceed. Thus, the delay

is equal to 256 instruction cycles. After exiting HALT, the Idle

Timer will return to being clocked by the low speed clock.

Note: To ensure accurate operation upon start-up of the

device using Multi-input Wake-up, the instruction in the ap-

plication program used for entering the HALT mode should

be followed by two consecutive NOP (no-operation) instruc-

tions.

13.4.1.5 Options

This device has two options associated with the HALT mode.

The first option enables the HALT mode feature, while the

second option disables HALT mode operation. Selecting the

disable HALT mode option will cause the microcontroller to

ignore any attempts to HALT the device under software

control. See 10.5 OPTION REGISTER for more details on

this option bit.

13.4.2 Dual Clock Idle Mode

In the IDLE mode, program execution stops and power

consumption is reduced to a very low level as with the HALT

mode. However, both oscillators, IDLE Timer (Timer T0), and

Clock Monitor continue to operate, allowing real time to be

maintained. The Idle Timer is clocked by the low speed

clock. The device remains idle for a selected amount of time

up to 1 second, and then automatically exits the IDLE mode

and returns to normal program execution using the high

speed clock.

The device is placed in the IDLE mode under software

control by setting the IDLE bit (bit 6 of the Port G data

The IDLE Timer window is selectable from one of five values,

0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second and

2 seconds. Selection of this value is made through the ITMR

The IDLE mode uses the on-chip IDLE Timer (Timer T0) to

keep track of elapsed time in the IDLE state. The IDLE Timer

runs continuously at the low speed clock rate, whether or not

the device is in the IDLE mode. Each time the bit of the timer

associated with the selected window toggles, the T0PND bit

is set, an interrupt is generated (if enabled), and the device

exits the IDLE mode if in that mode. If the IDLE Timer

interrupt is enabled, the interrupt is serviced before execu-

tion of the main program resumes. (However, the instruction

which was started as the part entered the IDLE mode is

completed before the interrupt is serviced. This instruction

should be a NOP which should follow the enter IDLE instruc-

tion.) The user must reset the IDLE Timer pending flag

(T0PND) before entering the IDLE mode.

As with the HALT mode, this device can also be returned to

normal operation with a Multi-Input Wake-up input.

The IDLE Timer cannot be started or stopped under software

control, and it is not memory mapped, so it cannot be read or

written by the software. Its state upon Reset is unknown.

Therefore, if the device is put into the IDLE mode at an

arbitrary time, it will stay in the IDLE mode for somewhere

between 30 µs and the selected time period.

In order to precisely time the duration of the IDLE state, entry

into the IDLE mode must be ”synchronized to the state of the

IDLE Timer. The best way to do this is to use the IDLE Timer

interrupt, which occurs on every underflow of the bit of the

COP8SCR9KMT7 Datasheet(PDF) 41 Page - National Semiconductor (TI)

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