COP8SCR9KMT7 datasheet(18/80 Pages) NSC

18 / 80 page

9.0 Pin Descriptions (Continued)

Writing a “1” to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G7 CKO Oscillator dedicated output

G6 SI (MICROWIRE/PLUS Serial Data Input)

G5 SK (MICROWIRE/PLUS Serial Clock)

G4 SO (MICROWIRE/PLUS Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

G0 INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake-Up feature on all eight

pins. Port L has the following alternate pin functions:

L7 Multi-Input Wake-up or T3B (Timer T3B Input)

L6 Multi-Input Wake-up or T3A (Timer T3A Input/Output)

L5 Multi-Input Wake-up or T2B (Timer T2B Input)

L4 Multi-Input Wake-up or T2A (Timer T2A Input/Output)

L3 Multi-Input Wake-up and/or RDX (USART Receive)

L2 Multi-Input Wake-up or TDX (USART Transmit)

L1 Multi-Input Wake-up and/or CKX (USART Clock) (Low

Speed Oscillator Output)

L0 Multi-Input Wake-up (Low Speed Oscillator Input)

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs

(except D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At

RESET, the external loads on this pin must ensure that the

output voltages stay above 0.7 V

CC to prevent the chip from

entering special modes. Also keep the external loading on

D2 to less than 1000 pF.

9.1 EMULATION CONNECTION

Connection to the emulation system is made viaa2x7

connector which interrupts the continuity of the RESET, G0,

G1, G2 and G3 signals between the COP8 device and the

rest of the target system (as shown in Figure 6). This con-

nector can be designed into the production pc board and can

be replaced by jumpers or signal traces when emulation is

no longer necessary. The emulator will replicate all functions

of G0 - G3 and RESET. For proper operation, no connection

should be made on the device side of the emulator connec-

tor.

10138906

FIGURE 3. I/O Port Configurations

10138907

FIGURE 4. I/O Port Configurations — Output Mode

10138908

FIGURE 5. I/O Port Configurations — Input Mode

COP8SCR9KMT7 Datasheet(PDF) 18 Page - National Semiconductor (TI)

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