DAC14135PCASM datasheet(7/12 Pages) NSC

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Digital Data Inputs

The DAC14135’s 14-bit binary inputs are CMOS compatible.

The input voltage thresholds are approximately half of the

digital supply voltage (DVDD/2). For a 3.3V DVDD, the

inputs are also compatible with standard TTL levels.

Digital data is standard binary coded, D13 is the most

signiﬁcant bit and D0 is the least signiﬁcant bit. For all 1’s

at the input, IOUTT = Ifullscale, IOUTF = 0. For all 0’s at the

input, IOUTT = 0, IOUTF = Ifullscale.

To prevent or reduce digital data feedthrough, keep digital

data lines short and ensure separate digital grounding

(DGND). 75

Ω resistors in series with the digital data input

path may be used to reduce overshoot and data

feedthrough to the analog outputs. Digital supply (DVDD)

should be decoupled to DGND using a 0.1

µF bypass

capacitor.

Driving the Clock Inputs

The differential clock inputs, Clock T and Clock F, may be

driven by a variety of input sources. These pins are

internally self-biased at about 1.5V and therefore can be

differentially AC coupled. Alternatively, a single clock

source on Clock T with Clock F bypassed to CGND using

a 0.1

µF capacitor, may be used to clock the DAC14135.

The clock driver supply voltage (CVDD) should be 5V

±5% and should be decoupled to the clock ground

(CGND) using a 0.1

µF capacitor. For best SFDR

performance, use a differential clock input. Minimum

input voltage swing (1.5Vpp) and slew rate (1.0V/ns)

requirements should be met for optimum performance.

Low noise and low jitter clocks provide the best SNR

performance for the DAC14135. Figure 1 shows one

method of driving the clock inputs. A low noise sinusoidal

clock source (2-4 Vpp) may be used to drive the trans-

former primary.

Figure 1: Method of Driving Clock Inputs

The transformer converts the single ended clock signal to

a differential signal. The diodes in the secondary limit the

input swing to the DAC14135.

Latching the Input Data

Inputs of the DAC14135 include a master-slave ﬂip-ﬂop.

Due to internal clock buffer delay, the DAC14135 requires

more hold time than setup time. This timing should be

observed at the DAC data and clock pins. Refer to the

timing diagram and the speciﬁcations for proper setup and

hold time requirements.

Data Scramble (DS) Input Pin

The DAC14135 is equipped with a data scramble input

pin (DS) that may be used to troubleshoot possible spuri-

ous or harmonic distortion degradation due to digital data

feedthrough

the

printed

circuit

board. In

the

DAC14135, the digital data inputs are logically XORed

with the DS input pin as shown in Figure 2.

Figure 2: Digital Data Inputs with DS Input Pin

If the DS pin is at logic low (DGND) the input data is left

unchanged and if this pin is at logic high (DVDD) the input

data is inverted. If the input data is XORed with a random

bit stream and if the same random bit stream is used to

drive the DS pin, low order harmonics due to data

feedthrough on the printed circuit board can be reduced.

If this feature is not used, tie DS pin to ground or leave it

ﬂoating (DS pin has internal active pulldown).

Voltage Reference Loop

The DAC14135 has an internal bandgap voltage

reference nominally at 1.235V. The output of this band-

gap is connected to the REFIO pin. The REFIO pin is a

high impedance output and therefore can be easily over-

D13

CLK

DAC14135

D12

•

Clock T

Clock F

Ω

0.1

µF

0.1

µF

0.1

µF

T1- 1T

DAC14135 Application Information

DAC14135PCASM Datasheet(PDF) 7 Page - National Semiconductor (TI)

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