VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

9

POST OFFICE BOX 655303

APPLICATION INFORMATION

† DIVDD is recommended to have a ferrite bead to filter the power transients.

NOTE: All analog outputs should be buffered if the load is resistive or if the load is capacitive with more than 2 pF loading.

The decoupling capacitors for the power supplies must be placed as close as possible to these terminals.

3 V

VSP1021PFB

AREA

CCD

SR Input

SV Input

CLAMP Input

DIVDD

DVDD

AVDD

3 V

1.8 V to 3.6 V

Ground

OBCLP Input

BLKG Input

ADCCLK Input

DAC1 Output

DAC2 Output

SCKP Input

RESET Input

STBY Input

SDIN Input

SCLK Input

CS Input

OE Input

AVDD

D[9−0]

DVDD

AVDD

1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

0.1

µF

1

µF

0.1

µF

0.1

µF

1

µF

1

µF

1

µF

DIVDD†

0.1

µF

AVDD

Video

Input

0.1

µF

0.1

µF

AVDD

RBD

RPD

RMD

AVDD

AVSS

OE

RESET

STBY

SCKP

CS

SDIN

SCLK

37

38

39

40

41

42

43

44

45

46

47

48

AVDD

CLAMP

SV

SR

OBCLP

BLKG

NC

DVDD

ADCCLK

DVSS

DIVSS

DIVDD

24

23

22

21

20

19

18

17

16

15

14

13

R

0.1

µF

AVDD

Figure 4. Typical Application Connection