VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

three-wire serial interface

A simple three-wire (SCLK, SDIN, and CS) serial interface is provided to allow writing to the internal registers

of the VSP1021 device. Serial clock SCLK can be run at a maximum speed of 40 MHz. Serial data SDIN is 16 bits

long. After 2 leading null bits, there are 4 address bits for which the internal register is to be updated; the following

10 bits are the data to be written to the register. Terminal 46 (CS) must be held low to enable the serial port. The

data transfer is initiated by the incoming SCLK after CS falls. Figure 3 shows the detailed timing for the serial

interface.

The SCLK polarity is selected by pulling terminal 45 (SCKP) either high or low.

device reset

The device is not under the default configuration after power on. The registers are set to the default value by

a reset. When terminal 43 (RESET) is pulled low, all internal registers are set to their default values. In addition,

the VSP1021 device has a software-reset function that resets the device when writing a control bit to control

register 1.

See the register definition section for the register default values.

power-down mode (standby)

The VSP1021 device implements both hardware and software power-down modes. Pulling terminal 44 (STBY)

low puts the device in the low-power standby mode. The total power drops to about 1 mW. Setting a power-down

control bit in the control register can also activate the power-down mode. Users can still program all internal

registers during the power-down mode.

power supply

The VSP1021 device has several power-supply terminals. Each major internal analog block has a dedicated

AVDD supply terminal. All internal digital circuitry is powered by DVDD. Both AVDD and DVDD are 3 V nominal.

Terminals 13 (DIVDD) and 14 (DIVSS) supply power to the output digital driver (D9−D0). DIVDD is independent

of DVDD and can be operated from 1.8 V to 3.6 V. This allows the outputs to interface with digital ASICs requiring

different supply voltages.

grounding and decoupling

General practices should apply to the printed-circuit-board (PCB) design to limit high-frequency transients and

noise that feed back into the supply and reference lines. This requires sufficient bypass of the supply and

reference terminals. In the case of power-supply decoupling, 0.1-

µF ceramic chip capacitors are adequate to

keep the impedance low over a wide frequency range. Recommended external decoupling for the three

voltage-reference terminals is shown in Figure 4. Since the effectiveness of the decoupling capacitors depends

largely on the proximity to the individual supply terminal, they must be placed as close as possible to these

terminals. An inductor is recommended for the DIVDD power supply (see Figure 4). Common ground level is

also recommended.

voltage references

An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage generates the ADC

Ref− voltage of 1 V and Ref+ of 2 V. It also generates the internal clamp voltage. All internally-generated voltages

are fixed values and cannot be adjusted. Terminals 37 (RBD), 38 (RPD), and 39 (RMD) must not be used to

drive any loads.