ADC12DS080 datasheet(7/34 Pages) TI1

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AGND

To Internal Circuitry

I/O

ADC12DS080

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SNAS443A – MARCH 2008 – REVISED MARCH 2013

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VDR = +3.0V, Internal VREF =

+1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤

TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Bits (min)

1.5

LSB (max)

INL

Integral Non Linearity

±0.5

-1.5

LSB (min)

0.5

LSB (max)

DNL

Differential Non Linearity

±0.25

-0.5

LSB (min)

PGE

Positive Gain Error

0.1

±1

%FS (max)

NGE

Negative Gain Error

0.1

±1

%FS (max)

VOFF

Offset Error

0.2

±0.65

%FS (max)

Under Range Output Code

Over Range Output Code

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

1.4

V (min)

VCMO

Common Mode Output Voltage

1.5

1.6

V (max)

1.4

V (min)

VCM

Analog Input Common Mode Voltage

1.5

1.6

V (max)

(CLK LOW)

8.5

VIN Input Capacitance (each pin to

CIN

VIN = 1.5 Vdc ± 0.5 V

GND)(4)

(CLK HIGH)

3.5

1.15

V (min)

VREF

Internal Reference Voltage

1.18

1.21

V (max)

TC VREF

Internal Reference Voltage Tempco

−40°C ≤ TA ≤ +85°C

ppm/°C

VRP

Internal Reference Top

2.0

VRN

Internal Reference Bottom

1.0

0.89

V (min)

Internal Reference Accuracy

(VRP-VRN)

0.97

1.06

V (max)

EXT

1.176

V (min)

External Reference Voltage

1.2

VREF

1.224

V (max)

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described

in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4)

The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

Figure 2.

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