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18 pF

13-Bit

210 MSPS

ADS5440

+ 5 V

THS4509

CM

348

Ω

348

Ω

100

Ω

100

Ω

78.9

Ω

From

50

Ω

Source

49.9

Ω

49.9

Ω

78.9

Ω

49.9

Ω

49.9

Ω

0.22

µF

0.22

µF

0.1

µF

0.1

µF

0.22

µF

Clock Inputs

CLK

ADS5440

CLK

Square Wave or

Sine Wave

0.01

µF

0.01

µF

ADS5440

SLAS467A – JULY 2005 – REVISED DECEMBER 2005

Application Information (continued)

Figure 37. Using the THS4509 With the ADS5440

Besides the OPA695, Texas Instruments offers a wide selection of single-ended operational amplifiers that can

be selected depending on the application. An RF gain block amplifier, such as Texas Instrument's THS9001, can

also be used with an RF transformer for high input frequency applications. For applications requiring dc-coupling

with the signal source, a differential input/differential output amplifier like the THS4509 (see Figure 37) is a good

solution as it minimizes board space and reduces the number of components.

In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to

differential, and sets the proper input common-mode voltage to the ADS5440.

The 50

Ω resistors and 18 pF capacitor between the THS4509 outputs and ADS5440 inputs (along with the input

capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (-3 dB).

Input termination is accomplished via the 78.9

Ω resistor and 0.22 µF capacitor to ground in conjunction with the

input impedance of the amplifier circuit. A 0.22

µF capacitor and 49.9 Ω resistor is inserted to ground across the

78.9

Ω resistor and 0.22 µF capacitor on the alternate input to balance the circuit.

Gain is a function of the source impedance, termination, and 348

Ω feedback resistor. See the THS4509 data

sheet for further component values to set proper 50

Ω termination for other common gains.

Since the ADS5440 recommended input common-mode voltage is +2.4 V, the THS4509 is operated from a

internal transistors of the THS4509.

The ADS5440 clock input can be driven with either a differential clock signal or a single-ended clock input, with

little or no difference in performance between both configurations. In low input frequency applications, where jitter

may not be a big concern, the use of single-ended clock (see Figure 38) could save some cost and board space

without any trade-off in performance. When driven on this configuration, it is best to connect CLK to ground with

a 0.01

µF capacitor, while CLK is ac-coupled with a 0.01 µF capacitor to the clock source, as shown in

Figure 38.

Figure 38. Single-Ended Clock

21

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