DP5380 datasheet(6/32 Pages) NSC

6 / 32 page

30 Register Description

31 GENERAL

The DP5380 ASI is a register-based device with eight ad-

dressable locations Some addresses have dual functions

depending upon whether they are being read from or written

to Device operation is described in Section 4

Figure 32 summarises the register map Note that for regis-

ters reading or writing SCSI signals the SCSI name is used

for each bit Although the SCSI bus is active low the regis-

ters invert the SCSI bus This means an active SCSI signal

is represented by a ONE in a register and an inactive signal

by a ZERO

32 REGISTERS

OUTPUT DATA REGISTER (ODR)

8 Bits

HA 0

Write-Only

This is a transparent latch used to send data to the SCSI

bus The register can be written by mP cycles or via DMA

DMA writes automatically select the ODR at Hex Address 0

(HA 0) This register is also written with the ID bits required

during arbitration and selectionreselection phases Data is

latched at the end of the write cycle

Bit 7

Bit 0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Output Data Register

CURRENT SCSI DATA (CSD)

8 Bits

HA 0

Read-Only

This register enables reading of the current SCSI data bus

If SCSI parity checking is enabled it will be checked at the

beginning of the read cycle The register is also used for mP

accesses of SCSI data during programmed-IO or ID check-

ing during arbitration Parity is not valid during arbitration

DMA transfers select the IDR (HA 6) instead of the CSD

Bit 7

Bit 0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Current SCSI Data

INITIATOR COMMAND REGISTER (ICR)

8 Bits

HA 1

Read-Write

This register is used to control the INITIATOR and some

other SCSI signals and to monitor the progress of bus arbi-

tration Most of the SCSI signals may also be asserted in

TARGET mode Bits 5 to 0 are reset when BSY is lost (see

MR2 description)

Bit 7

Bit 0

RST

TEST LADIFF

ACK

BSY

SEL ATN

DBUS

Initiator Command Register

DBUS Assert Data Bus

Bit 0

Disable SCSI data bus driving

Enable contents of Output Data Register onto the SCSI

data bus SCSI parity is also generated and driven on

DBP

This bit should be set when transferring data out of the ASI

in either TARGET or INITIATOR mode for both DMA or

programmed-IO In INITIATOR mode the drivers are only

enabled if Mode Register 2 TARGET MODE bit is 0 and

IO is false and CD IO MSG match the contents of the

Target Command Register (phasematch is true) In TAR-

GET mode only the MR2 bit needs to be set with this bit

Reading the ICR reflects the state of this bit

ATN Assert Attention

Bit 1

Deassert ATN

Assert SCSI ATN signal The MR2 TARGET MODE bit

must also be false to assert the signal

Reading the ICR reflects the state of this bit

SEL Assert Select

Bit 2

Deassert SEL

Assert SCSI SEL signal Can be used in INITIATOR or

TARGET mode

Reading the ICR reflects the state of this bit

BSY Assert Busy

Bit 3

Deassert BSY

Assert SCSI BSY signal Can be used in INITIATOR or

TARGET mode

Reading the ICR reflects the state of this bit

Hex

Mnemonic

Bits

Adr

Output Data Register

ODR

Current SCSI Data

CSD

Initator Command Register

ICR

Mode Register 2

MR2

Target Command Register

TCR

Select Enable Register

SER

Current SCSI Bus Status

CSB

Bus and Status

BSR

Start DMA Send

SDS

Start DMA Target Receive

SDT

Input Data Register

IDR

Start DMA Initiator Receive

SDI

Reset ParityInterrupts

RPI

FIGURE 32 Registers

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