DP5380 datasheet(15/32 Pages) NSC

15 / 32 page

70 Application Guide (Continued)

All the interface signal requirements are satisfied by a PAL

device The memory interface is not shown only the rele-

vant DMAC and mP lines are included

The ASI data and address lines connect directly to the mP

DMAC busses The DRQ output from the ASI goes direct to

the DMAC The EOP output from the DMAC goes to the ASI

input but can also be asserted via the PAL since the DMAC

output is open-drain

The PAL is programmed so that the mP can access the ASI

in three ways The three access types are Register RW

DMA RW DMA with EOP Examination of the PAL equa-

tions below shows how the mP may perform any of the three

basic access types simply by accessing the ASI at different

IO address slots This enables the mP to simulate a DMAC

(pseudo-DMA) DMA mode may then be used for all infor-

mation transfer phases

In DMA mode the ASI generates all SCSI handshakes At all

other times the mP is responsible for REQ ACK hand-

shakes Using pseudo-DMA may reduce mP overhead

When doing DMA transfers via BLOCK MODE and an error

occurs the ASI may not deassert the READY signal For

some DMA controllers this may lock the bus so the PAL

asserts READY and EOP to the DMA if an interrupt occurs

while READY is false This completes the current DMA cy-

cle and prevents further DMA for the rest of the block thus

allowing the bus to be handed back to the mP for servicing

The PAL generates RD and WR strobes while the mPisbus

master but the DMAC provides the strobes while it is bus

master so the PAL outputs are TRI-STATE

The PAL details are shown in

Figure 72 with the signal

definitions and equations following

TLF9756 – 10

FIGURE 72 Interface PAL

DP5380 Datasheet(PDF) 15 Page - National Semiconductor (TI)