DP5380V datasheet(10/32 Pages) NSC

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40 Device Operation (Continued)

device asserts SEL during arbitration If the LA bit is 0 the

data bus is read via the CSD register The data is examined

to resolve ID priorities If this device is the highest ID assert

SEL by setting ICR bit 2 to a 1 After waiting Bus Clear a

Bus Settle Delays (1200 ns) the Selection Phase begins

These 2 delays must be implemented in firmware

45 SELECTIONRESELECTION

The ASI can be used to select or reselect a device The ASI

will also respond to selection or reselection

451 SelectingReselecting

Selection requires programming the ODR with the desired

and own device ID’s the data bus via ICR DBUS (bit 0)

asserting ATN if required via ICR bit 1 asserting SEL via

ICR bit 2 then resetting the MR2 ARB bit

The SER should have been cleared to zero before Selec-

tionReselection to ensure the ASI does not respond If Re-

selection is desired the IO line should also be asserted

before SEL via TCR bit 0

Resetting the ARB bit causes the ASI to remove BSY and

the ODR from the data bus Thus the ICR Assert data bus

bit is required to assert the bits for desired and own device

ID’s

BSY is then monitored to determine when the device has

responded to (re)selection If the device fails to respond an

error handler should sequence the ASI off the bus If the

device responds the ICR DBUS and SEL bits should be re-

set to remove these signals If this is a Reselection the ICR

BSY bit (3) should be set before removing the other signals

The bus is now ready to handle Information Transfer Phas-

452 (Re)Selection Response

The ASI responds to Selection or Reselection when the

SER is non-zero A (re)selected interrupt is generated when

BSY is false for at least a Bus Settle Delay (400 ns) and

SEL is true AND any non-zero bit in the SER has its corre-

sponding SCSI data bus bit active A Selection is disabled

by zeroing the SER If parity is supported it should be valid

during (re)selection so must be checked via the SPE bit (5)

in the BSR SCSI specification states that (re)selection is

not valid if more than 2 data bits are active This condition is

checked by reading the CSD

When the selection interrupt occurs it is determined by read-

ing the BSR and CSB registers There is no dedicated

status bit for (re)selection so it must be determined by the

absence of other interrupts and the active state of the SEL

signal Reselection occurs when IO is also active See

Section 60

46 MONITORING BSY

While an INITIATOR is connected to a TARGET the TAR-

GET must maintain an active BSY signal During DMA oper-

ations the BSY signal is monitored by the ASI and will halt

operations if it goes inactive To enable BSY to be moni-

tored at other times the MR2 BSY bit (2) should be set An

interrupt will be generated if BSY goes inactive while MR2

BSY is set

This interrupt sets bit 2 in the BSR

47 COMMANDMESSAGESTATUS TRANSFERS

Command message and status bytes are transferred using

programmed-IO The SCSI REQ ACK handshake is ac-

complished by monitoring and setting lines individually Data

is output via the ODR and read in via the CSD register

The following code shows INITIATOR and TARGET pro-

gramming for two of these cases See Appendix A1 for

flowcharts

Initiator Command Send

MR2

4 monitor BSY

TCR

4 Command Phase

*02h*

while (bytes) to do)

while (REQ) inactive)

idle

*CSB bit 5

4 0*

if (BSR

phase match

44 0)

phase error

else

ODR

4 date byte

ICR

4 Assert ACK

while (REQ active)

idle

*CSB bit 5

44 1*

ICR

4 deassert ACK

* byte transfer complete *

byte count

goto data phase

Target Message Receive

* assumed Assert BSY already set in ICR *

MR2

4 TARG MODE OR PARITY CHECK OR

PARITY INTERRUPT

TCR

4 Message Out phase

*06h*

delay (Bus Settle)

TCR

4 Assert REQ

while (ACK inactive)

idle

* BSR bit 0 *

data e CSD

* parity is latched *

if (BSR

parity error)

error routine

else

TCR

4 deassert REQ

while (ACK active)

idle

* message done

can change to next

phase *

48 NON-BLOCK DMA TRANSFERS

Data transfers may be effected by DMA This method

should be used for optimum performance Two methods of

DMA are available-block and non-block mode This section

describes non-block mode transfers

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