DP5380V datasheet(14/32 Pages) NSC

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50 Interrupts (Continued)

If SCSI parity checking is enabled it will be checked and

should be valid Following an interrupt the BSR and CSD

should contain the values shown below

Bit 7

Bit 0

0001

EDMA DRQ SPER

INT

PHSM BSY

ATN

ACK

BSR

Bit 7

Bit 0

0000001

RST

BSY

REQ

MSG

SEL

DBP

CSD

60 Reset Conditions

61 GENERAL

There are three ways to reset the ASI mP chip RESET

SCSI bus reset applied externally SCSI bus reset issued by

the ASI

62 CHIP RESET

When the RESET signal is asserted for the required dura-

tion the ASI clears ALL internal registers and therefore re-

sets all logic This action does not create an interrupt or

generate a SCSI reset

63 EXTERNAL SCSI RESET

When a SCSI RST is applied externally the ASI resets all

registers and logic and issues an interrupt The only register

bits not affected are the Assert RST bit (bit 7) in the ICR and

the TARGET Mode bit (bit 6) in MR2

64 SCSI RESET ISSUED

When the mP sets the Assert RST bit in the ICR the RST

signal goes active Since the ASI monitors RST also the

same reset actions as in 63 apply The SCSI RST signal will

remain active as long as bit 7 in the ICR is setie until

programmed 0 or a chip RESET occurs

70 Application Guide

This section is intended to show the interface between the

P ASI and DMA controller (DMAC)

Figure 71 shows a

general interface when the ASI and DMAC are IO-mapped

devices This configuration will implementa2to 25M

Bytessec SCSI port using 2 cycle compressed timing from

the 5 MHz DMAC

Using a faster DMAC and memory may allow the ASI to

operate at a higher ratebut of course any system will be

limited by the available DMA rate from the SCSI device cur-

rently connected to The interface shown has several fea-

tures that are examined more closely in the following text

TLF9756 – 9

FIGURE 71 mPASIDMA Interface

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