4

2.0 Pin Description

DP83223 Pinout Summary

Symbol

Pin No

PLCC(PQFP)

Type

Description

13,26 (10, 25)

Supply

Vcc: Positive power supply for the ECL compatible circuitry. The

Transceiver operates from a single +5VDC power supply.

GND

14, 22(11 ,20)

Supply

GND: Return path for the ECL compatible circuitry power supply.

RXVcc

4, 27(26, 31)

Supply

Receive Vcc: Positive power supply for the small signal receive circuitry.

This power supply is intentionally separated from others to eliminate

receive errors due to coupled supply noise.

RXGND

3, 28(27, 30)

Supply

Receive GND: Return path for the receive power supply circuitry. This

power supply return is intentionally separated from others to eliminate

receive errors due to coupled supply noise.

TXVcc

5, 11(1, 7)

Supply

Transmit Vcc: Positive power supply required by the analog portion of the

transmit circuitry. This power supply is intentionally separated from the

others to prevent supply noise from coupling to the transmit outputs.

TXGND

7, 10(3, 6)

Supply

Transmit GND: Return path for the analog transmit power supply circuitry.

This supply return is intentionally separated from others to prevent supply

noise from being coupled to the transmit outputs.

EXTVcc

23(21)

Supply

External Vcc: Positive power supply for ECL output circuitry.

RXI+/-

2, 1(29, 28)

Differential

Voltage In

Receive Data Inputs: Balanced differential line receiver inputs.

PMID+/-

25, 24(23, 22)

ECL Out

Physical Media Indicate Data: Differential ECL compatible outputs

source the recovered receive data back to the Physical Layer device or to

a separate clock recovery device.

PMRD+/-

15, 16(12,13)

ECL In

Physical Media Request Data: Differential ECL compatible inputs which

receive data from Physical Layer Device.

TXO+/-

9, 8(5,4)

Differential

Current

Out

Transmit Data Outputs: Differential current driver outputs which drive

MLT-3 encoded data over twisted pair cable. These outputs provide

controlled rise and fall times designed to filter the transmitters output which

helps to reduce associated EMI.

SD+/-

20, 21(18, 19)

ECL Out

Signal Detect Outputs: Differential ECL compatible Signal Detect outputs

indicating that either a signal with the proper amplitude is present at the

RXI+/- inputs or that Loopback mode has been selected.

TXREF

6(2)

Current

Out

Transmit

Amplitude

Reference:

Reference

current

pin

allowing

adjustment of TXO+/- transmit amplitude. By placing a resistor between

this pin and GND, a reference current is setup which results in a given

transmit amplitude for a given application. Refer to Functional Description

in Section 3.1 for reference current equations.

ENCSEL

12(9)

CMOS In Encode Select Input: The TTL compatible CMOS Encode Select input

controls the encoded state of the signal at the TXO+/- outputs. A logic low

level at this input causes the TXO outputs to become MLT-3 encoded with

the receiver programmed to accept MLT-3 encoded data. This is the

recommended mode of operation. A logic high level causes the TXO pins

to output standard two-level binary code and the receiver is conditioned to

receive a two-level binary signal. The DP83223V does not guarantee this

mode(binary) of operation.

LBEN

19(17)

CMOS In Loopback Enable: TTL compatible CMOS Loopback Enable input pin

selects the internal loopback path which routes the PMRD+/- data to the

PMID+/- differential outputs and forces Signal Detect true. During

loopback, data present at the RXI+/- inputs is ignored. However, binary

data is still transmitted by the TXO+/- outputs (regardless of the state of the

ENCSEL input). Loopback mode is selected when LBEN is forced high.

Normal operation occurs when LBEN is forced low.