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DP83858 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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DP83858 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 37 page ![]() 18 http:\\www.national.com 4.4 Page Register (PAGE) 4.5 Partition Status Register (PARTITION) 4.6 Jabber Status Register (JABBER) 4.7 Administration Register (ADMIN) Page 0 Address 1h Page 1 Address 1h Bit Bit Name Access Bit Description D15 - D2 reserved — These bits are undefined when read. Must be written as 0. D1 - D0 PAGE[1:0] r/w These bits program the register page to be accessed. The page encoding is as follows: PAGE[1:0] Page 0h 0 (default) 1h 1 2h reserved 3h reserved Page 0 Address 2h Bit Bit Name Access Bit Description D15 - D12 reserved — These bits are undefined when read. D11 - D8 reserved — These bits are undefined when read. D7 - D0 JAB[7..0] read only The respective port's PART bit is set to 1 when Partitioning is sensed on that port. After reset, these bits are cleared to zero. Page 0 Address 3h Bit Bit Name Access Bit Description D15 - D12 reserved — These bits are undefined when read. D11 - D8 reserved — These bits are undefined when read. D7 - D0 JAB[7..0] read only The respective port's JAB bit is set to 1 when the Jabber condition is detected on that port. After reset, these bits are cleared to zero. Page 0 Address 4h Bit Bit Name Access Bit Description D15 - D13 reserved — For compatibility with future enhanced versions these bits must be written as zero. They are undefined when read. D12 TST_PART_LED r/w Test Partition LED: When this bit is set, the corresponding Partition LED logic will be enabled if any of the ADMIN_DIS bits are set. D11 - D8 reserved — These bits are undefined when read. D7 - D0 ADMIN_DIS[7] ... ADMIN_DIS[0] r/w Setting these bits to 0 enables the respective port (TX and RX). Writing a 1 to any bit will disable that port. Note that port enable/disable actions will occur at the next network idle period. For example, if an ADMIN_DIS bit is cleared dur- ing an incoming packet, this port will only be enabled after the incoming packet has finished. After reset, these bits default to zero (all ports enabled). |
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