PRELIMINARY DATA SHEET - Rev 1.0

04/2003

11

ACD2204

2

2

1

2

0

2

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

1

9

8

7

6

5

4

3

2

1

e

d

o

M

m

a

r

g

o

r

Pr

e

t

n

u

o

C

R

r

e

d

i

v

i

D

e

c

n

e

r

e

f

e

Rt

c

e

l

e

S

D

5

D

4

D

3

D

2

D

1

R

5

1

R

4

1

R

3

1

R

2

1

R

1

1

R

0

1

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

S

2

S

1

0000

1

00000000

1

00000000

000000000000000

1

0000

1

0

2

2

1

2

0

2

9

1

8

1

7

1

6

1

5

1

4

1

3

1

2

1

1

1

0

1

9

8

7

6

5

4

3

2

1

m

a

r

g

o

r

P

e

d

o

M

r

e

t

n

u

o

C

B

r

e

d

i

v

i

D

n

i

a

Mr

e

t

n

u

o

C

A

r

e

d

i

v

i

D

n

i

a

Mt

c

e

l

e

S

C

2

C

1

B

1

1

B

0

1

B

9

B

8

B

7

B

6

B

5

B

4

B

3

B

2

B

1

A

7

A

6

A

5

A

4

A

3

A

2

A

1

S

2

S

1

0

0

00

1

00000

1

0

0

0

1

00000

0

1

0

0

0000

11

000

11

0

0

0

1

1

0

0

1

1

LSB

MSB

LSB

MSB

For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison

Calculation of Main Divider Values

The values for the A and B counters are determined by the desired VCO output frequency for the local

oscillator and the phase detector comparison frequency:

N = f

B = trunc(N / P)

A = N - (B x P)

The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.

The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.

Phase Detector Polarity

Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be

In summary, for this example, the four register programming words are shown in Tables 16 and 17:

Table 16: PLL1 and PLL2 Reference Divider Register Bits

for Synthesizer Programming Example

Table 17: PLL1 and PLL2 Main Divider Register Bits

for Synthesizer Programming Example