AD7274 datasheet(6/20 Pages) AD

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REV. PrB

PRELIMINARYTECHNICALDATA

AD7273/AD7274

Preliminary Technical Data

Limit at TMIN, TMAX

Parameter

AD7273/AD7274

Units

Description

fSCLK

KHz min

MHz max

tCONVERT

14 x tSCLK

AD7274

12 x tSCLK

AD7273

tQUIET

T B D

ns min

Minimum Quiet Time required between Bus Relinquish

and start of Next Conversion

ns min

Minimum

CS Pulse Width

T B D

ns min

CS to SCLK Setup Time

T B D

ns max

Delay from

CS Until SDATA Three-State Disabled

T B D

ns max

Data Access Time After SCLK Falling Edge

0.4tSCLK

ns min

SCLK Low Pulse Width

0.4tSCLK

ns min

SCLK High Pulse Width

T B D

ns min

SCLK to Data Valid Hold Time

T B D

ns max

SCLK Falling Edge to SDATA Three-State

T B D

ns min

SCLK Falling Edge to SDATA Three-State

tpower-up

TBD

µs max

Power Up Time from Full Power-down

NOTES

1Guaranteed by Characterization. All input signals are specified with tr=tf=5ns (10% to 90% of V

DD) and timed from a voltage level of 1.6Volts.

2Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3Minimum

fsclk at which specifications are guaranteed.

4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the Vih or Vil voltage.

8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number

is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the

timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

6See Power-up Time section.

Specifications subject to change without notice.

TIMING SPECIFICATIONS1 (V

DD= +2.35 V to +3.6 V; VREF = 2.5V, TA= TMIN to TMAX, unless otherwise noted.)

Figure 1. Load Circuit for Digital Output

Timing Specifications

+1.6V

IOL

200µA

IOH

OUTPUT

25pF

SCLK

SDATA

SCLK

SDATA

1.6 V

SCLK

SDATA

Figure 2. Access time after SCLK falling edge

Figure 3. Hold time after SCLK falling edge

Figure 4. SCLK falling edge to SDATA Three-State

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