AD7274 datasheet(19/20 Pages) AD

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REV. PrB

PRELIMINARYTECHNICALDATA

Preliminary Technical Data

AD7273/AD7274

SERIAL INTERFACE

Figures 16 and 17 show the detailed timing diagram for

serial interfacing to the AD7274 and AD7273 respec-

tively. The serial clock provides the conversion clock and

also controls the transfer of information from the

AD7273/AD7274 during conversion.

The

CS signal initiates the data transfer and conversion

process. The falling edge of

CS puts the track and hold

into hold mode, takes the bus out of three-state and the

analog input is sampled at this point. The conversion is

also initiated at this point.

For the AD7274 the conversion will require 14 SCLK

cycles to complete. Once 13 SCLK falling edges have

elapsed the track and hold will go back into track on the

next SCLK rising edge as shown in Figure 16 at point B.

If the rising edge of

CS occurs before 14 SCLKs have

elapsed then the conversion will be terminated and the

SDATA line will go back into three-state. If 16 SCLKs

are considered in the cycle, the last two bits will be zeros

and

SDATA will return to three-state on the 16th SCLK

falling edge as shown in Figure 16.

For the AD7273 the conversion will require 12 SCLK

cycles to complete. Once 11 SCLK falling edges have

elapsed, the track and hold will go back into track on the

next SCLK rising edge, as shown in Figure 17 at point B.

If the rising edge of

CS occurs before 12 SCLKs have

elapsed then the conversion will be terminated and the

SDATA line will go back into three-state. If 16 SCLKs

are considered in the cycle, the AD7273 will clock out

four trailing zeros for the last four bits and SDATA will

Figure 16. AD7274 Serial Interface Timing Diagram

return to three-state on the 16th SCLK falling edge, as

shown in Figure 17.

If the user considers a 14 SCLKs cycle serial interface for

the AD7273/AD7274,

CS needs to be brought high after

the 14th SCLK falling edge, the last two trailing zeros

will be ignored and SDATA will go back into three-state.

In this case, a 45 MHz serial clock would allow to achieve

3MSPS throughput rate.

CS going low clocks out the first leading zero to be read

in by the microcontroller or DSP. The remaining data is

then clocked out by subsequent SCLK falling edges

beginning with the 2nd leading zero. Thus, the first fall-

ing clock edge on the serial clock has the first leading

zero provided and also clocks out the second leading zero.

The final bit in the data transfer is valid on the 16th fall-

ing edge, having being clocked out on the previous (15th)

falling edge.

In applications with a slower SCLK, it is possible to read

in data on each SCLK rising edge. In that case, the first

falling edge of SCLK will clock out the second leading

zero and it could be read in the first rising edge. However,

the first leading zero that was clocked out when

CS went

low will be missed unless it was not read in the first falling

edge. The 15th falling edge of SCLK will clock out the

last bit and it could be read in the 15th rising SCLK edge.

CS goes low just after one the SCLK falling edge has

elapsed,

CS will clock out the first leading zero as before

and it may be read in the SCLK rising edge. The next

SCLK falling edge will clock out the second leading zero

and it could be read in the following rising edge.

Figure 17. AD7273 Serial Interface Timing Diagram

SCLK

SDATA

2 LEADING

ZERO’S

THREE-

STATE

tquiet

tconvert

t 2

THREE-STATE

DB10

ZERO

1/ THROUGHPUT

DB11

DB9

ZERO

DB0

DB1

2TRAILING

ZE RO ’S

tquiet

THREE-STATE

ZERO

4TRAILING ZE RO’S

ZERO

SCLK

SDATA

2 LEADI NG

ZERO’S

THREE-

STATE

t 3

tconvert

DB8

ZERO

1/ THROUGHPUT

DB9

DB0

DB1

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