DP83901AV datasheet(43/62 Pages) NSC

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130 Bus Arbitration and Timing (Continued)

REMOTE WRITE TIMING

A Remote Write operation transfers data from the IO port

to the local buffer RAM The SNIC initiates a transfer by

requesting a byteword via the PRQ The system transfers a

byte-word to the latch via IOW this write strobe is detected

by the SNIC and PRQ is removed By removing the PRQ

the Remote DMA holds off further transfers into the latch

until the current byteword has been transferred from the

latch PRQ is reasserted and the next transfer can begin

1 SNIC asserts PRQ System writes byteword into latch

SNIC removes PRQ

2 Remote DMA reads contents of port and writes byte

word to local buffer memory increments address and

decrements byte count (RBCR0 1)

3 Go back to step 1

Steps 1 – 3 are repeated until the remote DMA is com-

plete

TLF10469 – 29

REMOTE DMA WRITE

Setting PRQ Using the Remote Read

Under certain conditions the SNIC’s bus state machine may

issue MWR and PRD before PRQ for the first DMA transfer

of a Remote Write Command If this occurs this could cause

data corruption or cause the remote DMA count to be dif-

ferent from the main CPU count causing the system to ‘‘lock

up’’

To prevent this condition when implementing a Remote

DMA Write the Remote DMA Write command should first

be preceded by a Remote DMA Read command to insure

that the PRQ signal is asserted before the SNIC starts its

port read cycle The reason for this is that the state machine

that asserts PRQ runs independently of the state machine

that controls the DMA signals The DMA machine assumes

that PRQ is asserted but actually may not be To remedy

this situation a single Remote Read cycle should be insert-

ed before the actual DMA Write Command is given This will

ensure that PRQ is asserted when the Remote DMA

Write is subsequently executed This single Remote Read

cycle is called a ‘‘dummy Remote Read’’ In order for the

dummy Remote Read cycle to operate correctly the Start

Address should be programmed to a known safe location in

the buffer memory space and the Remote Byte Count

should be programmed to a value greater than 1 This will

ensure that the master read cycle is performed safely elimi-

nating the possibility of data corruption

Remote Write with High Speed Buses

When implementing the Remote DMA Write solution with

high speed buses and CPU’s timing problems may cause

the system to hang Therefore additional considerations are

required

The problem occurs when the system can execute the dum-

my Remote Read and then start the Remote Write before

the SNIC has had a chance to execute the Remote Read If

this happens the PRQ signal will not get set and the Re-

mote Byte Count and Remote Start Address for the Remote

DP83901AV Datasheet(PDF) 43 Page - National Semiconductor (TI)

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