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DP83901AV Datasheet(PDF) 60 Page - National Semiconductor (TI) |
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DP83901AV Datasheet(HTML) 60 Page - National Semiconductor (TI) |
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60 / 62 page  150 Switching Characteristics AC Specs DP83901A Note All Timing is Preliminary (Continued) Remote DMA (Write Cycle) Recovery Time TLF10469 – 44 Symbol Parameter Min Max Units bprqh Bus Clock to Port Request High (Note 1) 42 ns wprql WACK to Port Request Low 50 ns wackw WACK Pulse Width 25 ns bprdl Bus Clock to Port Read Low (Note 2) 55 ns bprdh Bus Clock to Port Read High 40 ns wprq Remote Write Port Request to Port 12 BSCK Request Time (Notes 3 4 5) Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA cycles Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BSCK and whether a local DMA is pending Note 3 Assuming wackw k 1 BSCK and no local DMA interleave no CS immediate BACK and WACK goes high before T4 Note 4 WACK must be high for a minimum of 7 BSCK Note 5 This is not a measured value but guaranteed by design 60 |
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