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DS481 Datasheet(PDF) 9 Page - Texas Instruments |
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DS481 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 17 page ![]() DS481 www.ti.com SNLS131B – JULY 2000 – REVISED MARCH 2013 Unit Load A unit load for an RS-485 receiver is defined by the input current versus the input voltage curve. The gray shaded region is the defined operating range from −7V to +12V. The top border extending from −3V at 0 mA to +12V at +1 mA is defined as one unit load. Likewise, the bottom border extending from +5V at 0 mA to −7V at −0.8 mA is also defined as one unit load (see Figure 16 ). An RS-485 driver is capable of driving up to 32 unit loads. This allows up to 32 nodes on a single bus. Although sufficient for many applications, it is sometimes desirable to have even more nodes. The DS481 has ½ unit load and will allow up to 64 nodes guaranteed over temperature. For a ½ UL device the top and bottom borders shown in Figure 16 are scaled. Both 0 mA reference points at +5V and −3V stay the same. The other reference points are +12V at +0.5 mA for the top border and −7V at −0.4 mA for the bottom border (see Figure 16). Again, both 0 mA reference points at +5V and −3V stay the same. The other reference points are +12V at +0.25 mA for the top border and −7V at −0.2 mA for the bottom border (see Figure 16). The advantage of the ½ UL device is the increased number of nodes on one bus. In a single master multi-slave type of application where the number of slaves exceeds 32, the DS481 may save in the cost of extra devices like repeaters, extra media like cable, and/or extra components like resistors. Figure 16. Input Current vs Input Voltage Operating Range Sleep Mode The DS481 features an automatic sleep mode that allows the device to save power when not transmitting data. Since the sleep mode is automatic, no external components are required. It may be used as little or as much as the application requires. The more the feature is utilized, the more power it saves. The sleep mode is automatically entered when both the driver and receiver are disabled. This occurs when both the DE pin is asserted to a logic low and the RE(7) pin is asserted to a logic high. Once both pins are asserted the device will enter sleep mode after 50 ns. The DS481 is guaranteed to go into sleep mode within 600 ns after both pins are asserted. The device wakes up (comes out of sleep mode) when either the DE pin is asserted to a logic high and/or the RE(7) pin is asserted to a logic low. After the device enters sleep mode it will take longer for the device to wake up than it does for the device to enable from TRI-STATE. Refer to datasheet specifications tPSL and tPSH and compare with tPZL and t PZH for timing differences. The benefit of the DS481 is definitely its power savings. When active the device has a maximum ICC of 500 μA. When in sleep mode the device has a maximum ICC of only 10 μA, which is 50 times less power than when active. The ICC when the device is active is already very low but when in sleep mode the ICCis ultra low. (7) Non Terminated, Open Input only Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DS481 |
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