ADS5203IPFB datasheet(6/15 Pages) TI

6 / 15 page

ADS5203

SBAS258A – JUNE 2002 – REVISED JULY 2002

www.ti.com

TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Clock Rate

fCLK

MHz

Conversion Rate

MSPS

Clock Duty Cycle (40MHz)

Clock Duty Cycle (80MHz)

Output Delay Time

td(o)

CL = 10pF

Mux Setup Time

ts(m)

10.4

Mux Hold Time

th(m)

1.7

2.1

Output Setup Time

ts(o)

CL = 10pF

10.4

Output Hold Time

th(o)

CL = 10pF

1.5

2.2

Pipeline Delay (latency, channels A and B)

td(pipe)

MODE = 0, SELB = 0

CLK Cycles

Pipeline Delay (latency, channels A and B)

td(pipe)

MODE = 1, SELB = 0

CLK Cycles

Pipeline Delay (latency, channel A)

td(pipe)

MODE = 0, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel B)

td(pipe)

MODE = 0, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel A)

td(pipe)

MODE = 1, SELB = 1

CLK Cycles

Pipeline Delay (latency, channel B)

td(pipe)

MODE = 1, SELB = 1

CLK Cycles

Aperture Delay Time

td(a)

Aperture Jitter

tJ(a)

1.5

ps, rms

Disable Time, OE Rising to Hi–Ztdis

Enable Time, OE Falling to Valid Data

ten

TIMING OPTIONS

OPERATING MODE

MODE

SELB

TIMING DIAGRAM FIGURE

80MHz Input Clock, Dual-Bus Output, COUT = 40MHz

40MHz Input Clock, Dual-Bus Output, COUT = 40MHz

80MHz Input Clock, Single-Bus Output, COUT = 40MHz

80MHz Input Clock, Single-Bus Output, COUT = 80MHz

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