ADS5203

SBAS258A – JUNE 2002 – REVISED JULY 2002

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13

Table 2 lists the digital outputs for the corresponding

analog input voltages.

Table 2. Output Format for Single-Ended Configu-

ration.

SINGLE–ENDED INPUT, REFT – REFB = 1V

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

V(A/B+) = VCML + 1V

3FFH

V(A/B+) = VCML

200H

V(A/B+) = VCML – 1V

000H

REFERENCE TERMINALS

The ADS5203’s input range is determined by the voltages

on its REFB and REFT pins. The ADS5203 has an inter-

nal voltage reference generator that sets the ADC refer-

ence voltages REFB = 1V and REFT = 2V. The internal

plane. The recommended decoupling scheme is shown

in Figure 10. The internal reference voltages common-

mode voltage is 1.5V.

Figure 10. Recommended External Decoupling for

the Internal ADC Reference.

External ADC references can also be chosen. The

ADS5203 internal references must be disabled by tying

PWDN_REF

HIGH

before

applying

the

external

reference sources to the REFT and REFB pins. The

external

reference

voltages

common-mode

voltage

should be 1.5V for best ADC performance.

Figure 11. External ADC Reference Configuration.

DIGITAL INPUTS

Digital inputs are CLK, STDBY, PWDN_REF, OE, MODE,

and SELB. These inputs don’t have a pull-down resistor

to ground, therefore, they should not be left floating.

The CLK signal at high frequencies should be considered

Overshoot/undershoot should be minimized by proper

termination of the signal close to the ADS5203. An

important cause of performance degradation for a

high-speed ADC is clock jitter. Clock jitter causes

uncertainty in the sampling instant of the ADC, in addition

to the inherent uncertainty on the sampling instant caused

by the part itself, as specified by its aperture jitter. There

is a theoretical relationship between the frequency f and

one hand, and on the other hand the maximum amount

following relation:

As an example, for a 10-bit converter with a 20MHz input,

the jitter needs to be kept less than 7.8ps in order not to

have changes in the LSB of the ADC output due to the

total aperture error.

DIGITAL OUTPUTS

The output of ADS5203 is an unsigned binary code.

Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10pF is recommended)

to ensure best performance. Higher output loading

causes higher dynamic output currents and can,

therefore, increase noise coupling into the part’s analog

front end. To drive higher loads, the use of an output buffer

is recommended.

When clocking output data from ADS5203, it is important

timing section for detailed information on the pipeline

latency in the different modes.

to latch the output data, (see Figures 1 to 4). In Figure 4,

whether the data presently on the bus is from channel A

or B.

LAYOUT, DECOUPLING, AND GROUNDING

RULES

Proper grounding and layout of the PCB on which the

ADS5203 is populated is essential to achieve the stated

performance. It is advised to use separate analog and

digital ground planes that are spliced underneath the IC.

The ADS5203 has digital and analog pins on opposite

sides of the package to make this easier. Since there is

no connection internally between analog and digital

grounds, they have to be joined on the PCB. It is advised

to do this at one point in close proximity to the ADS5203.