DS99R101, DS99R102

SNLS240D – MARCH 2007 – REVISED APRIL 2013

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Electrical Characteristics

(1)(2)(3) (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

Output Differential Voltage

250

400

600

mV

VODSEL = L (Figure 10)

450

750

1200

mV

VODSEL = H (Figure 10)

Output Differential Voltage

4

50

mV

Unbalance

Offset Voltage

1.00

1.25

1.50

V

Offset Voltage Unbalance

1

50

mV

Output Short Circuit Current

DOUT = 0V, DIN = H,

TPWDNB, DEN = 2.4V,

−2

−5

−8

mA

VODSEL = L

DOUT = 0V, DIN = H,

TPWDNB, DEN = 2.4V,

−7

−10

−13

mA

VODSEL = H

TRI-STATE Output Current

TPWDNB, DEN = 0V,

−15

±1

+15

µA

DOUT = 0V or 2.4V

Serializer (Tx)

f = 40 MHz

Total Supply Current

VODSEL = L

40

80

mA

(includes load current)

Checker-board pattern (Figure 1)(6)

f = 40 MHz

VODSEL = H

40

85

mA

Checker-board pattern (Figure 1)(6)

Serializer (Tx)

TPWDNB = 0V

1

100

µA

Supply Current Power-down

(All other LVCMOS Inputs = 0V)

Deserializer (Rx)

f = 40 MHz

Total Supply Current

Checker-board pattern

95

mA

(includes load current)

(Figure 2)(6)

Deserializer (Rx)

f = 40 MHz

Total Supply Current

Random pattern

90

mA

(includes load current)

Deserializer (Rx)

RPWDNB = 0V

Supply Current Power-down

(All other LVCMOS Inputs = 0V,

1

50

µA

(5)

Digital, PLL, and Analog VDDs

(6)

Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).

Serializer Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Transmit Clock Period

Figure 5(1)

25

T

333

ns

Transmit Clock High Time

0.4T

0.5T

0.6T

ns

Transmit Clock Low Time

0.4T

0.5T

0.6T

ns

TCLK Input Transition Time

Figure 4

3

6

ns

TCLK Input Jitter

ps

33

(RMS)

(1)

Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).

(2)

4

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