4

AT49BV320C(T)

3372D–FLASH–5/04

Device

Operation

READ: When the AT49BV320C(T) is in the read mode, with CE and OE low and WE high, the

data stored at the memory location determined by the address pins are asserted on the out-

puts. The outputs are put in the high impedance state whenever CE or OE is high. This dual-

line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on, it will be in the read mode. In

order to perform other device functions, a series of command sequences are entered into the

device. The command sequences are shown in the “Command Definition” table on page 15

(I/O8 - I/O15 are don’t care inputs for the command codes). The command sequences are

written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and

OE high. The address and data are latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address locations used in the command

sequences are not affected by entering the command sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. When a high level is reasserted on the RESET pin, the device returns to the read mode,

depending upon the state of the control inputs.

ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The individual sectors can be erased by using the Sector Erase

command.

SECTOR ERASE: The device is organized into 71 sectors (SA0 - SA70) that can be individu-

ally erased. The Sector Erase command is a two-bus cycle operation. The sector address and

the D0H Data Input command are latched on the rising edge of WE. The sector erase starts

after the rising edge of WE of the second cycle provided the given sector has not been pro-

tected. The erase operation is internally controlled; it will automatically time to completion. The

maximum time to erase a sector is t

will result in the operation terminating immediately.

WORD PROGRAMMING: Once a memory sector is erased, it is programmed (to a logical “0”)

on a word-by-word basis. Programming is accomplished via the Internal Device command reg-

ister and is a two-bus cycle operation. The device will automatically generate the required

internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

time. If the program status bit is a “1”, the device was not able to verify that the program oper-

ation was performed successfully. The status register indicates the programming status. While

the program sequence executes, status bit I/O7 is “0”. While programming, the only valid com-

mands are Read Status Register, Program Suspend and Program Resume.

VPP PIN: The circuitry of the AT49BV320C(T) is designed so that the device cannot be pro-

grammed or erased if the V

program and erase operations can be performed. The VPP pin cannot be left floating.

READ STATUS REGISTER: The status register indicates the status of device operations and

the success/failure of that operation. The Read Status Register command causes subsequent

reads to output data from the status register until another command is issued. To return to

reading from the memory, issue a Read command.

The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H

when a Read Status Register command is issued.