SCAN25100

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SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013

POWER DOWN

When the transmitter is powered down by pulling pin TXPWDNB down, DOUT is put into a high impedance state.

When the receiver is powered down by pulling RXPWDNB down, ROUT[9:0], LOS, LOCKB, CDET, RXCLK, and

SYSCLK are high impedance. The MDC/MDIO signal pins are not powered down when TXPWDNB and/or

RXPWDNB are low.

Resetting the SCAN25100

The SCAN25100 has a rich set of hardware and software reset functions. When performing hardware pin resets,

TXPWDNB and RXPWDNB pins or the RESETB pin must be held low for at least 1 us.

Table 1. Reset Conditions

Reset Type

What is Reset

Initial power up

All internal states and registers held at reset for 150 ms after power on. This

reset period is based on an internal counter monitoring the 30.72 MHz REFCLK

input signal.

TXPWDNB and RXPWDNB low for

≥ 1 us

All internal states and registers are reset

RESETB low for

≥ 1 us

Logic reset (including MDIO)

Write “0” to MDIO RESETB register

Logic reset (excluding MDIO)

SPMODE change

Logic reset (excluding MDIO)

TXCLK missing for

≥ 7 cycles

Transmit FIFO flushed, transmit read/write pointers reset

RXCLK missing for

≥ 7 cycles (Read Mode)

Receive FIFO flushed, receive read/write pointers reset

TRSTB (IEEE 1149.1 interface)

Only IEEE 1149.1 state machine is reset

Deterministic FIFO Delay at Start Up

To ensure synchronous operation, REFCLK, TXCLK, and RXCLK should be stable and the receiver

synchronized before data is sent into or out of the parallel buses.

SCAN25100 CLOCK DOMAINS

Most SerDes have only two clocks: a reference clock (that also acts as a transmit clock) and a receive recovered

clock. The sharing of clocks in these architectures, however, can cause loss of lock issues during RE

synchronization. To provide seamless base station synchronization, the SCAN25100 features independent

transmit and receive PLLs and four clock signals.

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