Philips Semiconductors

Product data

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

2002 Feb 22

17

2.4.3

Programming the IF Reference Divider <B21:B12>

The IF phase detector’s reference input is an integer multiple of the frequency at the input of the REFin pin. The reference divider has 10

programmable bits, <B21:B12> for allowable divide ratios, R, from 4 to 1023 when the 3 bit binary SA counter (refer to section 2.5.1) is set to all

zeros. Table 10 lists the allowable R values.

Table 10. R Values for the IF Reference Divider

<B21>

<B20>

<B19>

<B18>

<B17>

<B16>

<B15>

<B14>

<B13>

<B12>

R

0

0

0

0

0

0

0

1

0

0

4

0

0

0

0

0

0

0

1

0

1

5

0

0

0

0

0

0

0

1

1

0

6

—

—

—

—

—

—

—

—

—

—

…

1

1

1

1

1

1

1

1

1

0

1022

1

1

1

1

1

1

1

1

1

1

1023

2.5

C-word Register

Table 11. C-word, length 24 bits

Last IN

<21>

<20>

<19>

<18>

<17>

<16>

<15>

<14>

<13>

<12>

<11>

<10>

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

IF Divider An

CP

Lock detect

Reset

bit

SA

1

0

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CP1

CP0

L1

L0

Tsigrst

SA2

SA1

SA0

Default:

0

0

0

0

0

1

1

1

0

0

1

0

1

0

1

1

0

0

0

0

0

0

C-word address

Fixed to 10

A-Divider

A0..A13, IF divider values , see section “characteristics for allowed for divider ratios.

Charge pump current

Ratio

CP1, CP0: Charge pump current ratio, see table of charge pump currents.

Lock detect

See Table 13.

Reset bit

1

→ Tsigrst : resets the sigma-delta modulator after each loading of an A-word.

( It is held in the reset state between the first and second falling edge of the RF divider output pulse

after STROBE has gone high at the end of the A-word. )

IF comparison select

SA Comparison divider select for IF phase detector

2.5.1

Programming the SA Counter <C2:C0>

The 3 bit SA register determines which of the 5 divider outputs (refer to table 11) is selected as the IF phase detector’s input (see Figure 5).

Table 12. IF phase comparator frequency

<C2>

<C1>

<C0>

Divide Ratio

IF Phase Comparator Frequency

0

0

0

R

0

0

1

R * 2

0

1

0

R * 4

0

1

1

R * 8

1

0

0

R * 16

NOTES:

2.5.2

Programming the Reset Bits <B11>, <C3>

The reset bits offer extra flexibility. The default value for bits <B11>, <C3> are all zeros. Bit <B11> disables the IF reference divider and allows

for extra savings of approximately 200

µA when set to ‘1’. However, this bit must initially be set to ‘0’ during any power-up sequence. The RF

phase detector is activated after a delay of four edges of the reference divider output clock. Bit <C3> resets the sigma-delta modulator after

each loading of an A-word. It is held in the reset state between the first and second falling edge of the RF divider output pulse after STROBE

has gone high at the end of the A-word.