THS8200 datasheet(29/97 Pages) TI

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4–14

f – Frequency – Rad

–4

–3

–2

–1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

MAGNITUDE

FREQUENCY

Figure 4–14. IFIR Phase Response

Each of the two interpolation stages can be switched in or bypassed:

•

a 4:2:2 input mode is selected on DMAN).

•

× to 2× interpolation stage and can be set active for optional 2×

interpolation when an input format with pixel clock < 80 MSPS is present.

4.7

Display Timing Generator (DTG)

4.7.1

Overview of Functionality

THS8200 can generate dedicated Hsync/Vsync/FieldID video synchronization outputs, as well as a composite sync

inserted on either the G/Y or all analog output channels. Both types of output synchronization can be available

simultaneously and programmed independently. Synchronization patterns are fully programmable to accommodate

all standard VESA (PC graphics) and ATSC (DTV) formats as well as nonstandard formats.

For the purpose of output video timing generation, the device is configured in HDTV, SDTV or VESA mode

(dtg1_mode register). Depending on the selected DTG mode, a number of line types are available to generate the

full video frame format. The timing and position of horizontal and vertical syncs, the position of horizontal and vertical

blanking intervals, and the structure, position and width of equalization pulses, pre- and post-serration pulses within

the vertical blanking interval are user-programmable.

The DTG determines:

•

the frame format/field format (number of pixels/line, number of lines/field1, number of lines/field2, number

of fields/frame = 1 for progressive or 2 for interlaced formats) and its synchronization to the input data source

–

registers: dtg1_total_pixels, dtg1_linecnt, dtg1_frame_size, dtg1_field_size

•

in slave mode, whether HS_IN, VS_IN, FID (dedicated sync inputs) are used for input video synchronization

or video timing is extracted from embedded SAV/EAV codes, as well as the relative position of the video

frame with respect to these synchronization signals

–

registers: dtg2_embedded_timing, dtg2_hs_in_dly, dtg2_vs_in_dly

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