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MB9B160L Datasheet(PDF) 97 Page - Cypress Semiconductor |
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MB9B160L Datasheet(HTML) 97 Page - Cypress Semiconductor |
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97 / 118 page  Document Number: 002-04976 Rev.*A Page 97 of 118 MB9B160L Series 12.4.13 I 2C Timing Typical Mode, High-speed Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Typical Mode High-speed Mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)* 1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock "L" width tLOW 4.7 - 1.3 - μs SCL clock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45* 2 0 0.9* 3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP 2 MHz ≤ tCYCP<40 MHz 2tCYCP* 4 - 2tCYCP* 4 - ns *5 40 MHz ≤ tCYCP<60 MHz 4tCYCP* 4 - 4tCYCP* 4 - ns 60 MHz ≤ tCYCP<80 MHz 6tCYCP*4 - 6tCYCP* 4 - ns 80 MHz ≤ tCYCP<100 MHz 8tCYCP* 4 - 8tCYCP* 4 - ns 100 MHz ≤ tCYCP<120 MHz 10tCYCP* 4 - 10tCYCP* 4 - ns 120 MHz ≤ tCYCP<140 MHz 12tCYCP* 4 - 12tCYCP* 4 - ns 140 MHz ≤ tCYCP<160 MHz 14tCYCP* 4 - 14tCYCP* 4 - ns 160 MHz ≤ tCYCP<180 MHz 16tCYCP* 4 - 16tCYCP* 4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: A high-speed mode I 2C bus device can be used on a typical mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I 2C is connected to, see "8. Block Diagram" in this data sheet. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. |
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