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IN

CLK

IN

CDCM1804

VBB

VBB − Bias voltage output

S0087-01

DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING

Output Behavior From Enabling the Device (EN = 0

→ 1)

CDCM1804

SCAS697E – JULY 2003 – REVISED MAY 2005

APPLICATION INFORMATION (continued)

Figure 14. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1804

In disable mode (EN = 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also

switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500

µA.

When the device is enabled again, it takes typically 1

µs for the settling of the reference voltage and currents.

During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. Y3 is unknown (could be high or low). After the

settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the

input clock, the state of the waveforms after enabling the device is as shown in Figure 15. The inverting input

and output signal are not included. The Y:/1 waveform is the undivided output driver state.

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