 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LM3561 Datasheet(PDF) 5 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LM3561 Datasheet(HTML) 5 Page - Texas Instruments |
|
|
5 / 37 page  LM3561 www.ti.com SNOSB44C – MARCH 2011 – REVISED MAY 2013 Electrical Characteristics (continued) Limits in standard typeface are for TA = +25°C. Limits in boldface type apply over the full operating ambient temperature range (-40°C ≤ TA ≤ +85ºC). Unless otherwise specified, VIN = 3.6V, VHWEN = VIN. (1) (2) Parameter Test Conditions Min Typ Max Unit 2.7V ≤ VIN ≤ 5.5V, HWEN = IN, ISTBY Standby supply current 1.1 2.3 µA Enable Register bit [1:0] = 00 Flash-to-torch LED current TX_ Low-to-High, 2 settling time ILED = 600mA to 93.2mA tTX µs Torch-to-flash LED current TX_ Low-to-High, 80 settling time ILED = 93.2mA to 600mA VIN Falling, VIN_TH VIN monitor trip threshold VIN Monitor Register = 0x01 2.84 2.90 2.95 V (Enabled with VIN_TH = 2.9V) HWEN, STROBE, TX1/TORCH/GPIO1, TX2/INT/GPIO2 Voltage Specifications VIL Input logic low 2.7V ≤ VIN ≤ 5.5V 0 0.4 V VIH Input logic high 2.7V ≤ VIN ≤ 5.5V 1.2 VIN V Output logic low VOL ILOAD = 3mA, 2.7V ≤ VIN ≤ 5.5V 0.4 V (GPIO1,GPIO2, INT) Internal pulldown resistance at RTX1 300 k Ω TX1/TORCH/GPIO1 Internal pulldown resistance at RTX2 300 k Ω TX2/GPIO2 Internal pulldown resistance at RSTROBE 300 k Ω STROBE I2C-Compatible Voltage Specifications (SCL, SDA) VIL Input Logic Low 2.7V ≤ VIN ≤ 5.5V 0 0.4 V VIH Input Logic High 2.7V ≤ VIN ≤ 5.5V 1.3 VIN V VOL Output Logic Low (SDA) ILOAD = 3mA, 2.7V ≤ VIN ≤ 5.5V 400 mV I2C-Compatible Timing Specifications (SCL, SDA) (5) see Figure 4 fSCL SCL(Clock Frequency) 0 400 kHz Rise Time of Both SDA and 20 + 0.1 × tRISE (7) 300 ns SCL CBUS 20 + 0.1 × tFALL (8) Fall Time of Both SDA and SCL 300 ns CBUS tLOW Low Period of SCL Clock 1.3 µs tHIGH High Period of SCL Clock 600 ns Hold Time for Start (or tHD;STA 600 ns Repeated Start) Condition Set-up Time for a Repeated tSU;STA 600 ns Start tHD;DAT Data Hold Time 0 ns tSU;DAT Data Setup Time 100 ns tSU;STO Set-up Time for Stop Condition 600 ns tVD;DAT Data Valid Time 900 ns tVD;ACK Data Valid Acknowledge Time 900 ns Bus Free Time Between a Start tBUF 1.3 µs and a Stop Condition (7) Min rise and fall times on SDA and SCL can typically be less than 20ns. (8) Min rise and fall times on SDA and SCL can typically be less than 20ns. Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LM3561 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
