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LM5175PWPR Datasheet(PDF) 16 Page - Texas Instruments |
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LM5175PWPR Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 38 page ![]() sw T 1 200 ns F R 37 pF § · ¨ ¸ © ¹ CL(AVG) SNS 50 mV I R 16 LM5175 SNVSA37A – OCTOBER 2015 – REVISED MAY 2016 www.ti.com Product Folder Links: LM5175 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Feature Description (continued) 8.3.5 Overcurrent Protection The LM5175 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions. In buck operation, the sensed valley voltage across the CSG and CS pins is limited to 76 mV. The high-side buck switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time. In boost operation, the maximum peak voltage across CS and CSG is limited to 170mV. If the peak current in the low-side boost switch causes the CS pin to exceed this threshold voltage, the boost switch is turned off for the remainder of the clock cycle. Applying the appropriate voltage to the MODE pin of the LM5175 enables hiccup mode fault protection (see MODE Pin Configuration). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current limiting for 128 consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is automatically released after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is not enabled through the MODE pin, the LM5175 will operate in cycle-by-cycle current limiting as long as the overload condition persists. 8.3.6 Average Input/Output Current Limiting The LM5175 provides optional average current limiting capability to limit either the input or the output current of the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected in series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50 mV reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the soft-start capacitor. When the soft-start capacitor discharges below the 0.8-V feedback reference voltage VREF, the output voltage of the converter decreases to limit the input or output current. The average current limiting feature can be used in applications requiring a regulated current from the input supply or into the load. The target constant current is given by Equation 4: (4) The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together. 8.3.7 CCM/DCM Operation The LM5175 allows selection of continuous conduction mode (CCM) or discontinuous conduction mode (DCM) operation using the MODE pin (see MODE Pin Configuration). In CCM operation the inductor current can flow in either direction and the controller switches at a fixed frequency regardless of the load current. This mode is useful for noise-sensitive applications where a fixed switching eases filter design. In DCM operation the synchronous rectifier MOSFETs emulate diodes as LDRV1 or HDRV2 turn-off for the remainder of the PWM cycle when the inductor current reaches zero. The DCM mode results in reduced frequency operation at light loads, which lowers switching losses and increases light load efficiency of the converter. 8.3.8 Frequency and Synchronization (RT/SYNC) The LM5175 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from the RT/SYNC pin to AGND. The RT resistor is related to the nominal switching frequency (Fsw) by the following equation: (5) Figure 3 in the Typical Characteristics shows the relationship between the programmed switching frequency (Fsw) and the RT resistor. The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The external synchronization pulse is ac coupled using a capacitor to the RT/SYNC pin. The voltage at the RT/SYNC pin must not exceed 3.3 V peak. The external synchronization pulse frequency should be higher than the internally set oscillator frequency and the pulse width should be between 75 ns and 500 ns. |
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