UTRON

UT62256C

Rev. 1.0

32K X 8 BIT LOW POWER CMOS SRAM

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

3



CAPACITANCE (TA=25℃, f=1.0MHz)

PARAMETER

SYMBOL

MIN.

MAX

UNIT

Input Capacitance

-

8

pF

Input/Output Capacitance

-

10

pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0V to 3.0V

Input Rise and Fall Times

5ns

Input and Output Timing Reference Levels

1.5V

Output Load

(1) READ CYCLE

PARAMETER

SYMBOL

UT62256C-35

UT62256C-70

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

35

-

70

-

ns

Address Access Time

-

35

-

70

ns

Chip Enable Access Time

-

35

-

70

ns

Output Enable Access Time

-

25

-

35

ns

Chip Enable to Output in Low Z

10

-

10

-

ns

Output Enable to Output in Low Z

5

-

5

-

ns

Chip Disable to Output in High Z

-

25

-

35

ns

Output Disable to Output in High Z

-

25

-

35

ns

Output Hold from Address Change

5

-

5

-

ns

(2) WRITE CYCLE

PARAMETER

SYMBOL

UT62256C-35

UT62256C-70

UNIT

MIN.

MAX.

MIN.

MAX.

Write Cycle Time

35

-

70

-

ns

Address Valid to End of Write

30

-

60

-

ns

Chip Enable to End of Write

30

-

60

-

ns

Address Set-up Time

0

-

0

-

ns

Write Pulse Width

25

-

50

-

ns

Write Recovery Time

0

-

0

-

ns

Data to Write Time Overlap

20

-

30

-

ns

Data Hold from End of Write Time

0

-

0

-

ns

Output Active from End of Write

5

-

5

-

ns

Write to Output in High Z

-

15

-

25

ns

*These parameters are guaranteed by device characterization, but not production tested.