DAC488HR datasheet(2/4 Pages) ETC

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DAC488HR

™

General Information

DAC488HR Design

Four independent analog output modules are optically isolated

from the IEEE 488 bus, digital circuitry, earth ground, and

chassis common by up to 500 VDC. Each module consists of a

microcontroller and expandable data buffer. A common update

clock is shared by all ports, ensuring synchronization. Four

internal clock sources are available to meet a wide variety of

applications including CD and DAT testing. An external clock

source (up to 10 MHz) allows synchronization to an external

frequency reference and can be used to synchronize the

DAC488HR to the ADC488A series (see p. 243) digitizers for

stimulus/response applications.

Multiple Trigger Sources

All DAC488HR ports share a common trigger source, ensuring

multi-channel synchronization for applications with critical

time and phase relationships. Trigger sources for the DAC488HR

include trigger command, IEEE 488 Group Execute Trigger

(GET), and external TTL (rising or falling edge) signal input.

Triggers can also be initiated on periodic intervals from 2 ms to

65,535 ms, specified in 1 ms increments. The DAC488HR pro-

vides a delayed TTL-level trigger output for stimulus/response

applications in which the device under test (DUT) must attain a

steady state prior to measurement. This function allows users to

specify a time delay, in update clock counts from 1 to 65,535,

between the DAC488HR’s output and the trigger signal’s output.

Multiple Clock Sources

The DAC488HR features four internal clock sources and accommo-

dates an external clock source (up to 10 MHz) for updating the

output ports. A 16-bit counter is used to provide update rates to

meet application requirements. For example, the 200-kHz clock

and the 5-MHz clock can be divided down to any rate between 3 Hz

and 100 kHz for general purpose applications; the

5.6448-MHz clock can simulate 44.1-kHz audio CD signals; and the

6.144-MHz can simulate 48-kHz audio DAT signals. For synchro-

nizing external circuitry to DAC488HR output, an update clock

signal is also provided.

Buffer Management

The DAC488HR’s step, burst, waveform, and continuous trigger

output modes can be used with flexible buffer management

functions to output stepped voltages, any one of five standard

waveforms, or user-defined arbitrary waveforms. Waveforms are

loaded from the IEEE 488 bus into the DAC488HR’s resident

8 Ksample buffer at rates up to 500 Kbytes/s.

To output standard predefined sine, square, and triangle wave-

forms, the user specifies the starting memory location, number

of samples, max/min values, duty cycle, and the number of

times the cycle is to be repeated or “looped.” The “looping”

function outputs specified buffer segments up to the full avail-

able buffered size for repetition up to 65,535 times. This con-

serves memory space by allowing long periodic waveforms to be

defined in a single cycle. Additionally, for applications that

exceed the DAC488HR’s internal buffer capacity, waveforms

can be output continuously from an IEEE 488 controller at up to

200 Kbytes/s via the IEEE 488 bus.

Nonvolatile Storage

The DAC488HR uses resident nonvolatile random access

memory (NVRAM) to store the calibration constants deter-

mined during digital calibration, and to store its power-up

default configuration.

Each DAC488HR output port features a separate microprocessor and

buffer memory for independent waveform management

D/A

channel 3

D/A

channel 1

Isolated

analog

output

Non-isolated

digital I/O

IEEE 488

interface

Internal

peripheral

interface

bus

D/A

channel 2

D/A

channel 4

Non-

isolated

Isolated

Power

source 1

Power

source 2

Power

source 3

Power

source 4

main

Main

processor

digital

circuitry

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