Unused Input

Input

Output

Input

Unused Input

Output

Frequency - MHz

0

10

20

30

40

50

60

0

50

100

150

200

250

300

D003

SN54LVC540A, SN74LVC540A

www.ti.com

SCAS297N – JANUARY 1993 – REVISED JUNE 2014

Typical Application (continued)

10.2.3 Application Curves

11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the

Recommended Operating Conditions table.

supply, 0.1

each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1

μF

and a 1

μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as

possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions

of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only

3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages

at the outside connections result in undefined operational states. Specified below are the rules that must be

observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low

bias to prevent them from floating. The logic level that should be applied to any particular unused input depends

convenient. It is generally OK to float outputs unless the part is a transceiver. If the transceiver has an output

enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of

the IO’s so they also cannot float when disabled.

12.2 Layout Example

Figure 7. Layout Diagram

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