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LM9810 Datasheet(PDF) 11 Page - Texas Instruments |
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LM9810 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 22 page ![]() Pin Descriptions (Continued) D1 b7, b7, b1, b1 D0 b6, b6, b0, b0 Input Mode (NewLine High) D5-D3 Don’t Care D2 (SCLK) Serial Data Clock. D1 (Latch) Latch and Shift Enable Signal. When D1(Latch) is low, data is shifted into D0(SDI). When D1(Latch) goes high, the last nine bits shifted into D0(SDI) will be used to program the addressed configuration register. To avoid erroneous writes to the configuration registers, D1(Latch) should be pulled low when NewLine is high. D0 (SDI) Serial Input Data. Data is valid on D2(SCLK) rising edge. Three address bits followed by six data bits (MSB first) should be shifted into D0 before D1(Latch) goes high. Timing Diagrams DS100943-73 FIGURE 1. Pixel Conversion Timing and Latency DS100943-74 FIGURE 2. SampCLK and Output Data Timing (NewLine Low) www.national.com 10 |
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