Valid Data

SDI

16

SCLK

Valid Data

LMP91050

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SNAS517E – NOVEMBER 2011 – REVISED SEPTEMBER 2015

Timing Characteristics (continued)

(1)

PARAMETER

TEST CONDITIONS

UNIT

Wake-up time

1

ms

Serial clock frequency

10

MHz

SCLK pulse width high

ns

SCLK pulse width low

ns

CSB set-up time

10

ns

CSB hold time

10

ns

SDI set-up time prior to rise

10

ns

edge of SCLK

SDI hold time prior to rise edge

10

ns

of SCLK

SDO disable time after rise

45

ns

edge of CSB

45

ns

edge of SCLK

SDO enable time from the fall

35

ns

SDO access time after the fall

35

ns

edge of SCLK

SDO hold time after the fall

5

ns

edge of SCLK

SDO rise time

5

ns

SDO fall time

5

ns

(2)

Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using

statistical quality control (SQC) method.

(3)

Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

Figure 1. SPI Timing Diagram

Figure 2. SPI Set-Up Hold Time

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