 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST7FLCD1 Datasheet(PDF) 34 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7FLCD1 Datasheet(HTML) 34 Page - STMicroelectronics |
|
|
34 / 95 page  Clocks & Low Power Modes ST7FLCD1 34/95 6.2.4 Selected Peripherals Mode Certain peripherals have an “On/Off “bit to disconnect the block (or part of it) and decrease MCU power consumption. Figure 15: WAIT Flow Chart Table 9: Peripheral Modes Bits Register Comment Default at Reset PORTs PxDDi PxDDR Cut the output function pad (input mode) OFF ADC ADON ADCSR Cut analog consumption and clock OFF PWMi OEi PWMCRx Cut the pad consumption OFF DDC PE, DDC2BPE DDCCR, DDCDCR OFF WDG WGDA WDGCR Cut the output reset OFF I2C PE I2CCR OFF Note: Before servicing an interrupt, the CC register is pushed on the stack. The I bit is set during the interrupt routine and cleared when the CC register is popped. If reset Fetch Reset, Vector or Service Interrupt MDP Run Mode N N Interrupt Reset WFI instruction 4096 CPU Clock Cycles Delay Y Y MCU Oscillator: ON Periph. clock: ON CPU clock: ON I bit: Cleared Oscillator: ON Periph. clock: ON CPU clock: ON I bit: Set |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
