LP2975 datasheet(21/37 Pages) TI1

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LP2975

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SNVS006F – SEPTEMBER 1997 – REVISED APRIL 2013

It is important to note that RO is a function of input supply voltage (see Figure 22. As shown, the minimum value

of RO is about 550Ω @ VIN = 24V, increasing to about 1.55 kΩ @ VIN = 3V.

Using the equation for fpg, a family of curves are provided showing how fpg varies with CEFF for several values of

RO (see Figure 23).

Figure 23. fpg vs. CEFF

As can be seen in the graph, values of CEFF in the 500 pF–2500 pF range produce values for fpg between 40 kHz

and 700 kHz. To determine what effect fpg will have on stability, the bandwidth of the regulator loop must be

calculated (see next section, Crossover Frequency and Phase Margin).

Crossover Frequency and Phase Margin

The term fc will be used to define the crossover frequency of the regulator loop (which is the frequency where the

gain curve crosses the 0 dB axis). The importance of this frequency is that it is the point where the loop gain

goes below unity, which marks the usable bandwidth of the regulator loop.

It is the phase margin (or lack of it) at fc that determines whether the regulator is stable. Phase margin is defined

as the total phase shift subtracted from 180°. In general, a stable loop requires at least 20°-30° of phase margin

at fc.

fc can be approximated by the following equation (all terms have been previously defined):

This equation assumes that no CF is used and fpg/fc > 1.

If the frequency of the Gate capacitance pole fpg has been calculated (previous section), the amount of added

phase shift may now be determined. As shown in the graph below (see Figure 24, the amount of added phase

shift increases as fpg approaches fc.

The amount of phase shift due to fpg that can occur before oscillation takes place depends on how much added

phase shift is present as a result of the COUT pole (see previous section, Output Capacitor).

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