LP3923

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SNVS567B – APRIL 2010 – REVISED MAY 2013

LP3923 Serial Port Communication: Slave Address Code: 7h'7E

Register

Addr

D7

D6

D5

D4

D3

D2

D1

D0

(Default value)*

OP_EN1

BUCK_

EN_

8h'00

X

X

EN_LDO8

EN_LDO7

EN_LDO2

EN_LDO1

(01000111)

PWM

BUCK

LDO1PGM O/P

SEL=BATT

LDO1_

LDO1_

LDO1_

LDO1_

LDO1_

8h'01

(00001100)

X

X

X

V1_OP[4]

V1_OP[3]

V1_OP[2]

V1_OP[1]

V1_OP[0]

SEL=GND

(00011011)

LDO2 Program O/P

SEL=BATT

LDO2_

LDO2_

LDO2_

LDO2_

LDO2_

8h'02

(00001100)

X

X

X

V2_OP[4]

V2_OP[3]

V2_OP[2]

V2_OP[1]

V2_OP[0]

SEL=GND

(00011011)

LDO3 PGM O/P

LDO3_

LDO3_

LDO3_

LDO3_

LDO3_

8h'03

X

X

X

(00011011)

V3_OP[4]

V3_OP[3]

V3_OP[2]

V3_OP[1]

V3_OP[0]

LDO4 PGM O/P

LDO4_

LDO4_

LDO4_

LDO4_

LDO4_

8h'04

X

X

X

(00011011)

V4_OP[4]

V4_OP[3]

V4_OP[2]

V4_OP[1]

V4_OP[0]

LDO5 PGM O/P

LDO5_

LDO5_

LDO5_

LDO5_

LDO5_

8h'05

X

X

X

(00011011)

V5_OP[4]

V5_OP[3]

V5_OP[2]

V5_OP[1]

V5_OP[0]

LDO6 PGM O/P

LDO6_

LDO6_

LDO6_

LDO6_

LDO6_

8h'06

X

X

X

(00011011)

V6_OP[4]

V6_OP[3]

V6_OP[2]

V6_OP[1]

V6_OP[0]

LDO7 PGM O/P

LDO7_

LDO7_

LDO7_

LDO7_

LDO7_

8h'07

X

X

X

(00011011)

V7_OP[4]

V7_OP[3]

V7_OP[2]

V7_OP[1]

V7_OP[0]

LDO8 PGM O/P

LDO8_

LDO8_

LDO8_

LDO8_

LDO8_

8h'08

X

X

X

(00011011)

V8_OP[4]

V8_OP[3]

V8_OP[2]

V8_OP[1]

V8_OP[0]

Status1

Trig.-

PWR_ON(10000010)

PWR_ON

HF_PWR

CHG_IN

8h'0C

Trig.-

X

TSD_H

TSD_L

FF

X

TRIG

TRIG

TRIG

HF_PWR(01000010)

Trig.-CHG_IN

(00100010)

PROG_

PROG_

CHARGER Control 1

Force_

8h'10

X

X

CHGTIME[1 CHGTIME[0

EN_EOC

X

EN_CHG

(00010 001)

EOC

]

]

CHARGER Control 2

PROG_

PROG_

PROG_

PROG_

PROG_

8h'11

X

X

X

(00000111)

ICHG[4]

ICHG[3]

ICHG[2]

ICHG[1]

ICHG[0]

CHARGER Control 3

VTERM[

PROG_

PROG_

PROG_

PROG_

8h'12

X

X

VTERM[0]

(00011001)

1]

EOC[1]

EOC[0]

VSTRT[1]

VSTART[0]

CHARGER Status 1

BATT_

CHGIN_

TOUT_

TOUT_

8h'13

EOC

X

FULLRATE

PRECHG

(0000 0000)

OVER_OUT

OK_OUT

FULLRATE

PRECHG

CHARGER Status 2

TOUT_

8h'14

X

X

X

X

X

X

BAD_BATT

(00000000)

CONSTV

MISC Control1

EN_

PS_HOLD_

8h'1C

X

X

X

X

X

X

(00000000)

APU_TSD

DELAY

(1)

X — Not used.

BOLD locations are Read Only type.

NOTE: All Control registers apart from Charger Control registers (h'10 — h'12) are reset to default at the end of every Power Down

sequence.

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