Silan

Semiconductors

SC9257

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

REV: 1.0

2001.10.18

21

Lock detection bits

The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock

bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference

frequency and divided output of programmable counter. These systems also have phase error detection bits ( bits

PE1~PE3), which are capable of more precise detection (

±0.55µs~±7.15µs).

1.

Unlock detection bit (UNLOCK)

This bit detects, using the reference frequency cycle, the phase difference between the reference

frequency and the divided output of the programmable counter. When there is no lock, that is, when the

reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set.

Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock

F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of

the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a

time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference

frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked

state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is

reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing.

That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.

"H" level

High impedance

"L" level

Reference frequency

Programmable

counter output

DO output

Phase comparator

Lock detection strobe

Unlock is reset (RESET)

Unlock F/F (UNLOCK)

Lock enable (ENABLE)

Phase error detection

Counts phase difference.

Fig.10