ST16C450IP40 datasheet(13/28 Pages) EXAR

13 / 28 page

ST16C450

Rev. 4.20

Transmit and Receive Holding Register

The serial transmitter section consists of an 8-bit

Transmit Hold Register (THR) and Transmit Shift

the Line Status Register (LSR). Writing to the THR

transfers the contents of the data bus (D7-D0) to the

THR, providing that the THR or TSR is empty. The

THR empty flag in the LSR register will be set to a logic

1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can

be performed when the transmit holding register

empty flag is set.

The serial receive section also contains an 8-bit

Receive Holding Register, RHR. Receive data is

removed from the ST16C450 and receive by reading

the RHR register. The receive section provides a

mechanism to prevent false starts. On the falling edge

of a start or false start bit, an internal receiver counter

starts counting clocks at 16x clock rate. After 7 1/2

clocks the start bit time should be shifted to the center

of the start bit. At this time the start bit is sampled and

if it is still a logic 0 it is validated. Evaluating the start

bit in this manner prevents the receiver from assem-

bling a false character. Receiver status codes will be

posted in the LSR.

Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the inter-

rupts from receiver ready, transmitter empty, line

status and modem status registers. These interrupts

would normally be seen on the ST16C450 INT output

pin.

IER BIT-0:

Logic 0 = Disable the receiver ready interrupt. (normal

default condition)

Logic 1 = Enable the receiver ready interrupt.

IER BIT-1:

Logic 0 = Disable the transmitter empty interrupt.

(normal default condition)

Logic 1 = Enable the transmitter empty interrupt.

IER BIT-2:

Logic 0 = Disable the receiver line status interrupt.

(normal default condition)

Logic 1 = Enable the receiver line status interrupt.

IER BIT-3:

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

IER BIT 4-7: Not used and set to “0”.

Interrupt Status Register (ISR)

The ST16C450 provides four levels of prioritized

interrupts to minimize external software interaction.

The Interrupt Status Register (ISR) provides the user

with four interrupt status bits. Performing a read cycle

on the ISR will provide the user with the highest

pending interrupt level to be serviced. No other inter-

rupts are acknowledged until the pending interrupt is

serviced. Whenever the interrupt status register is

read, the interrupt status is cleared. However it should

be noted that only the current pending interrupt is

cleared by the read. A lower level interrupt may be seen

after rereading the interrupt status bits. The Interrupt

Source Table 5 (below) shows the data values (bit 0-3)

for the four prioritized interrupt levels and the interrupt

sources associated with each of these interrupt levels:

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