TMS320C6421 datasheet(74/222 Pages) TI1

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3.5.1.1 EMIFA Pinout Mode (AEM[2:0])

3.5.1.2 FASTBOOT PLL Multiplier Select (PLLMS)

3.5.1.3 Endianess Selection (LENDIAN)

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346D – JANUARY 2007 – REVISED JUNE 2008

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pins only during device reset. The user must take care of any potential data contention in the system. To

help avoid system data contention, the C6421 puts these configuration pins into a high-impedance state

(Hi-Z) when device reset (RESET or POR) is asserted, and continues to hold them in a high-impedance

state until the internal global reset is removed; at which point, the default peripheral (either GPIO or

EMIFA based on default of AEM[2:0]) will now control these pins.

All of the device boot and configuration pin settings are captured in the corresponding bit fields in the

BOOTCFG register (see Section 3.4.2.1, BOOTCFG Register).

The following subsections provide more details on the device configurations determined at device reset:

AEM, PLLMS, and LENDIAN.

To support different usage scenarios, the C6421 provides intricate pin multiplexing between the EMIFA

and other peripherals. The PINMUX0.AEM register bit field in the System Module determines the EMIFA

Pinout Mode. The AEM[2:0] pins only select the default EMIFA Pinout Mode. It is latched at device reset

de-assertion (high) into the BOOTCFG.DAEM bit field. The AEM[2:0] value also sets the default of the

PINMUX0.AEM bit field. While the BOOTCFG.DAEM bit field shows the actual latched value and cannot

be modified, the PINMUX0.AEM value can be changed by software to modify the EMIFA Pinout Mode.

Note: The AEM[2:0] value does not affect the operation of the EMIFA module itself. It only affects which

EMIFA pins are brought out to the device pins. For more details on the AEM settings, see Section 3.7,

Multiplexed Pin Configurations.

If FASTBOOT = 1, the PLLMS[2:0] pins select PLL multiplier for Fastboot modes. If FASTBOOT = 0, the

PLLMS[2:0] pins are ignored.

The PLLMS[2:0] pin values are latched at device reset de-assertion into the BOOTCFG.PLLMS field and

cannot be modified by software. This value is only applicable during fast boot.

For more information on boot modes and the FASTBOOT PLL multiplier selection, see Section 3.4.1, Boot

Modes.

The LENDIAN configuration pin latched at reset determines the endianess setting of the device. If

LENDIAN = 1, little endian is selected. If LENDIAN = 0, big endian is selected.

The setting is latched and stored in the BOOTCFG.LENDIAN field and cannot be modified by software.

Device Configurations

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TMS320C6421 Datasheet(PDF) 74 Page - Texas Instruments