TMS320C6421 datasheet(85/222 Pages) TI1

85 / 222 page

TMS320C6421

Fixed-Point Digital Signal Processor

www.ti.com

SPRS346D – JANUARY 2007 – REVISED JUNE 2008

Table 3-18. PINMUX1 Register Description (continued)

Bit

Field Name

Description

Pins Controlled

PWM1 Block Pin Select.

Selects the function of the multiplexed pins in the PWM1 Block.

0 = GPIO Mode (default).

PWM1 Block:

PWM1BK

Pin functions as GPIO (GP[4]).

GP[4]/PWM1

1 = PWM1 Mode.

Pin functions as PWM1.

UART0 Flow Control Block Pin Select.

Selects the function of the multiplexed pins in the UART0 Flow Control Block.

00 = GPIO Mode (default).

Pins function as GPIO (GP[88:87]).

UART0 Flow Control Block:

11:10

UR0FCBK

01 = UART0 Flow Control Mode.

UCTS0/GP[87]

Pins function as UART0 Flow Control UCTS0 and URTS0.

URTS0/PWM0/GP[88]

10 = PWM0 + GPIO Mode.

Pins function as PWM0 and GPIO (GP[87]).

11 = Reserved

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

–

(default).

UART0 Data Block Pin Select.

Selects the function of the multiplexed pins in the UART0 Data Block.

UART0 Data Block:

0 = GPIO Mode (default).

UR0DBK

URXD0/GP[85]

Pins function as GPIO (GP[86:85]).

UTXD0/GP[86]

1 = UART0 Data Mode.

Pins function as UART0 data URXD0 and UTXD0.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

–

(default).

Host Block:

VLYNQ_CLOCK/GP[57]

HD0/VLYNQ_SCRUN/GP[58]

Host Block Pin Select.

HD1/VLYNQ_RXD0/GP[59]

If EMAC opertaion is desired, EMAC must be placed in reset before

HD2/VLYNQ_RXD1/GP[60]

programminng PINMUX1. HOSTBK or PINMUX0.RMII to select EMAC pins.

HD3/VLYNQ_RXD2/GP[61]

HOSTBK = 000: GPIO Mode

HD4/VLYNQ_RXD3/GP[62]

Pins function as GPIO (GP[83:57]).

HD5/VLYNQ_TXD0/GP[63]

HD6/VLYNQ_TXD1/GP[64]

HOSTBK = 001: HPI + 1 GPIO Mode.

HD7/VLYNQ_TXD2/GP[65]

Pins function as HPI and GPIO (GP[57]).

HD8/VLYNQ_TXD3/GP[66]

HD9/MCOL/GP[67]

HOSTBK = 010: VLYNQ + 17 GPIO Mode.

HD10/MCRS/GP[68]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD11/MTXD3/GP[69]

VLYNQ_TXD[3:0]), and GP[83:67].

HD12/MTXD2/GP[70]

6:4

HOSTBK

HD13/MTXD1/GP[71]

HOSTBK = 011: VLYNQ + MII + MDIO Mode.

HD14/MTXD0/GP[72]

Pins function as VLYNQ (VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_RXD[3:0],

HD15/MTXCLK/GP[73]

VLYNQ_TXD[3:0]), MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

HHWIL/MRXDV/GP[74]

RXCLK, RXD[3:0]), and MDIO (MDIO, MDC).

HCNTL1/MTXEN/GP[75]

When EMAC(MII) is selected, EMAC(RMII) must not be selected.

HCNTL0/MRXER/GP[76]

PINMUX0.RMII must be set to 0.

HR/W/MRXCLK/GP[77]

HOSTBK = 100: MII + MDIO +10 GPIO Mode.

HDS2/MRXD0/GP[78]

Pins function as MII (TXCLK, CRS, COL, TXD[3:0], RXVD, TXEN, RXER,

HDS1/MRXD1/GP[79]

RXCLK, RXD[3:0]), MDIO (MDIO, MDC), and GP[66:57].

HRDY/MRXD2/GP[80]

When EMAC(MII) is selected, EMAC(RMII) must not be selected.

HCS/MDCLK/GP[81]

PINMUX0.RMII must be set to 0.

HINT/MRXD3/GP[82]

HAS/MDIO/GP[83]

All other HOSTBK combinations reserved.

The HOSTBK field selects the function of these

27 pins.

Reserved. For proper device operation, the user should only write "0" to this bit

3:1

RESERVED

–

(default).

RSV

Reserved. Writes have no effect.

–

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