TMS320VC5504 datasheet(7/123 Pages) TI1

7 / 123 page

TMS320VC5504

www.ti.com

SPRS609B – JUNE 2009 – REVISED JANUARY 2010

Table 3-1. Characteristics of the VC5504 Processor (continued)

HARDWARE FEATURES

VC5504

PLL Options

Software Programmable Multiplier

x4 to x4099 multiplier

BGA Package

10 x 10 mm

196-Pin BGA (ZCH)

Process Technology

0.09 mm

Product Preview (PP),

Product Status (1)

Advance Information (AI),

or Production Data (PD)

(1)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

3.2

C55x CPU

The TMS320VC5504 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation

processor core. The C55x DSP architecture achieves high performance and low power through increased

parallelism and total focus on power savings. The CPU supports an internal bus structure that is

composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read

buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These

buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA

controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit

multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional

16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel

activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit

(DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The

Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a

128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit

decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.

Predictive branching capability avoids pipeline flushes on execution of conditional instructions calls.

For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide

(literature number SWPU073).

The C55x core of the VC5504 can address 16M bytes of unified data and program space. It also

addresses 64K words of I/O space. The VC5504 includes three types of on-chip memory: 128 KB

read-only memory (ROM), 192 KB single-access random access memory (SARAM), 64 KB dual-access

random access memory (DARAM). The memory map is shown in Figure 3-1.

Device Overview

Submit Documentation Feedback

Product Folder Link(s): TMS320VC5504

TMS320VC5504 Datasheet(PDF) 7 Page - Texas Instruments

TMS320VC5504 Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL