TMS320VC5504 datasheet(73/123 Pages) TI1

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TMS320VC5504

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SPRS609B – JUNE 2009 – REVISED JANUARY 2010

Table 6-12. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory(1) (2) (see Figure 6-15 and

Figure 6-17)(3)

CVDD = 1.05 V

DVDDEMIF = 3.3/2.8/2.5/1.8 V

NO.

PARAMETER

UNIT

MIN

NOM

MAX

READS and WRITES

td(TURNAROUND)

Turn around time

(TA)*E - 9

(TA)*E

(TA)*E + 9

READS

EMIF read cycle time (EW = 0)

(RS+RST+RH)*E - 9

(RS+RST+RH)*E

(RS+RST+RH)*E + 9

tc(EMRCYCLE)

EMIF read cycle time (EW = 1)

(RS+RST+RH+(EWC*16))*E - 9

(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 9

Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)

(RS)*E-9

(RS)*E

(RS)*E+9

tsu(EMCEL-EMOEL)

Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)

-9

Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)

(RH)*E - 9

(RH)*E

(RH)*E + 9

th(EMOEH-EMCEH)

Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1)

-9

tsu(EMBAV-EMOEL)

Output setup time, EM_BA[1:0] valid to EM_OE low

(RS)*E-9

(RS)*E

(RS)*E+9

th(EMOEH-EMBAIV)

Output hold time, EM_OE high to EM_BA[1:0] invalid

(RH)*E-9

(RH)*E

(RH)*E+9

tsu(EMBAV-EMOEL)

Output setup time, EM_A[20:0] valid to EM_OE low

(RS)*E-9

(RS)*E

(RS)*E+9

th(EMOEH-EMAIV)

Output hold time, EM_OE high to EM_A[20:0] invalid

(RH)*E-9

(RH)*E

(RH)*E+9

EM_OE active low width (EW = 0)

(RST)*E-9

(RST)*E

(RST)*E+9

tw(EMOEL)

EM_OE active low width (EW = 1)

(RST+(EWC*16))*E-9

(RST+(EWC*16))*E

(RST+(EWC*16))*E+9

td(EMWAITH-EMOEH)

Delay time from EM_WAITx deasserted to EM_OE high

4E-9

4E+9

WRITES

EMIF write cycle time (EW = 0)

(WS+WST+WH)*E-9

(WS+WST+WH)*E

(WS+WST+WH)*E+9

tc(EMWCYCLE)

(WS+WST+WH+(EWC*16))*E -

(WS+WST+WH+(EWC*16))*E +

EMIF write cycle time (EW = 1)

(WS+WST+WH+(EWC*16))*E

Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)

(WS)*E - 9

(WS)*E

(WS)*E + 9

tsu(EMCSL-EMWEL)

Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)

-9

Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)

(WH)*E-9

(WH)*E

(WH)*E+9

th(EMWEH-EMCSH)

Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)

-9

tsu(EMBAV-EMWEL)

Output setup time, EM_BA[1:0] valid to EM_WE low

(WS)*E-9

(WS)*E

(WS)*E+9

th(EMWEH-EMBAIV)

Output hold time, EM_WE high to EM_BA[1:0] invalid

(WH)*E-9

(WH)*E

(WH)*E+9

tsu(EMAV-EMWEL)

Output setup time, EM_A[20:0] valid to EM_WE low

(WS)*E-9

(WS)*E

(WS)*E+9

th(EMWEH-EMAIV)

Output hold time, EM_WE high to EM_A[20:0] invalid

(WH)*E-9

(WH)*E

(WH)*E+9

(1)

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These

parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.

(2)

E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For example,

when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.

(3)

EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified

by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.

Peripheral Information and Electrical Specifications

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