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TMS570LS0914 Datasheet(PDF) 53 Page - Texas Instruments |
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TMS570LS0914 Datasheet(HTML) 53 Page - Texas Instruments |
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53 / 159 page  /NR /1 to /64 OSCIN PLL INTCLK /OD /1 to /8 VCOCLK /R /1 to /32 post_ODCLK /NF /1 to /256 PLLCLK fPLLCLK = (fOSCIN / NR) * NF / (OD * R) TMS570LS0914 www.ti.com SPNS225C – JUNE 2013 – REVISED SEPTEMBER 2015 Table 6-10. LPO Specifications PARAMETER MIN TYP MAX UNIT Clock Detection oscillator fail frequency - lower threshold, using 1.375 2.4 4.875 MHz untrimmed LPO output oscillator fail frequency - higher threshold, using 22 38.4 78 MHz untrimmed LPO output LPO - HF oscillator untrimmed frequency 5.5 9 19.5 MHz trimmed frequency 8 9.6 11 MHz startup time from STANDBY (LPO BIAS_EN High for 10 µs at least 900µs) cold startup time 900 µs LPO - LF oscillator untrimmed frequency 36 85 180 kHz startup time from STANDBY (LPO BIAS_EN High for 100 µs at least 900µs) cold startup time 2000 µs 6.6.1.3 Phase Locked Loop (PLL) Clock Module The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. • Configurable frequency multipliers and dividers. • Built-in PLL Slip monitoring circuit. • Option to reset the device on a PLL slip detection. 6.6.1.3.1 Block Diagram Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller. Figure 6-6. PLL Block Diagram 6.6.1.3.2 PLL Timing Specifications Table 6-11. PLL Timing Specifications PARAMETER MIN MAX UNIT fINTCLK PLL1 Reference Clock frequency 1 20 MHz Post-ODCLK – PLL1 Post-divider input clock fpost_ODCLK 400 MHz frequency VCOCLK – PLL1 Output Divider (OD) input clock fVCOCLK 150 550 MHz frequency Copyright © 2013–2015, Texas Instruments Incorporated System Information and Electrical Specifications 53 Submit Documentation Feedback Product Folder Links: TMS570LS0914 |
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