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TMS570LS0914 Datasheet(PDF) 93 Page - Texas Instruments |
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TMS570LS0914 Datasheet(HTML) 93 Page - Texas Instruments |
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93 / 159 page  VCCIO VIH VIH VIL 0 Input tpw VIL TMS570LS0914 www.ti.com SPNS225C – JUNE 2013 – REVISED SEPTEMBER 2015 7 Peripheral Information and Electrical Specifications 7.1 I/O Timings 7.1.1 Input Timings Figure 7-1. TTL-Level Inputs Table 7-1. Timing Requirements for Inputs(1) Parameter MIN MAX Unit tpw Input minimum pulse width tc(VCLK) + 10 (2) ns tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns (1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK) (2) The timing shown above is only valid for pin used in general-purpose input mode. 7.1.2 Output Timings Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (CL) Parameter MIN MAX Unit Rise time, tr 8mA low EMI pins CL = 15 pF 2.5 ns (see Table 4-40) CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Fall time, tf CL = 15 pF 2.5 ns CL = 50 pF 4 CL = 100 pF 7.2 CL = 150 pF 12.5 Rise time, tr 4mA low EMI pins CL = 15 pF 5.6 ns (see Table 4-40) CL = 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Fall time, tf CL = 15 pF 5.6 ns CL= 50 pF 10.4 CL = 100 pF 16.8 CL = 150 pF 23.2 Rise time, tr 2mA-z low EMI pins CL = 15 pF 8 ns (see Table 4-40) CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Fall time, tf CL = 15 pF 8 ns CL = 50 pF 15 CL = 100 pF 23 CL = 150 pF 33 Copyright © 2013–2015, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 93 Submit Documentation Feedback Product Folder Links: TMS570LS0914 |
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